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operational description july 2002 tfec0410g 2.5/10 gbits/s optical networking interface with strong/weak fec and digital wrapper 1 document organization this document is primarily intended for designers who require design implementation information and block interface specifications. this is a companion document to the tfec0410g document group, which consists of the following documents: tfec0410g product description tfec0410g operational description tfec0410g hardware register memory map tfec0410g hardware design guide tfec0410g system design guide this document contains the following information divided into the following sections: block diagrams (section 3 on page 23) device overview (section 2 on page 6) top-level overview (section 4 on page 29) dw and fec (section 5 on page 37?section 18 on page 112) sonet fec (bch weak/in band) supermacro (section 19 on page 113) bch macro (section 20 on page 118) bch overhead processing (section 21 on page 128?section 37 on page 166) microprocessor interface (section 38 on page 167) tfec primary clock inputs (section 39 on page 179) tfec clock multiplexers (section 40 on page 180) tfec data multiplexers (section 41 on page 182) tfec phase detectors (section 42 on page 183) tfec loopbacks (section 43 on page 185) tfec valid modes (section 44 on page 186) outline diagram (section 45 on page 187) list of acronyms (section 46 on page 188) ordering information (section 47 on page 203)
table of contents contents page 2 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 1 document organization ......................................................................................................... ............................... 1 2 device overview............................................................................................................... .................................... 6 2.1 device modes overview ....................................................................................................... .......................... 8 2.2 system interface overview ................................................................................................... .......................... 9 2.3 section/line overhead insert/drop overview (figure 3) ........................................................................ ........ 9 2.4 toac insert/drop channel overview ........................................................................................... ................ 10 2.4.1 mode 1?full toac drop/insert mode ......................................................................................... .......... 10 2.4.2 mode 2?partial insert/drop mode ........................................................................................... ............... 12 2.5 in-band (weak) fec overview (bose-chaudhuri-hocquenghem (bch-3))................................................. 13 2.6 strong fec (g.975) and digital wrapper (otn) processing overview........................................................ 14 2.6.1 elastic stores (es) ....................................................................................................... ........................... 14 2.6.2 rs encoder/decoder and digital wrapper basis frame format ............................................................ 15 2.6.3 fec overhead and digital wrapper overhead definition ...................................................................... .17 2.6.4 fec/dw?dwac (digital wrapper access channel) drop/insert block ................................................ 18 2.6.5 receive/transmit fec/dw framer............................................................................................ ............. 19 2.7 line interface?mux/demux overview ........................................................................................... ............ 19 2.8 alarm status output signals overview ........................................................................................ ................. 20 2.9 microprocessor interface overview........................................................................................... .................... 20 2.9.1 transfer error acknowledge (tea_n) (with mpc860 and mc68360 only) ............................................ 20 2.9.2 interrupt structure....................................................................................................... ............................. 20 2.10 clocking overview .......................................................................................................... ............................ 21 3 block diagrams................................................................................................................ ................................... 23 4 top-level overview............................................................................................................ ................................ 29 4.1 top-level functionality ..................................................................................................... ............................ 29 4.2 top-level clocking .......................................................................................................... ............................. 29 4.3 top-level loss-of-clock detectors........................................................................................... .................... 31 4.4 top-level reset architecture (hardware/software) ............................................................................ ......... 32 4.5 top-level loopback control signals .......................................................................................... .................. 33 4.6 top-level powerup control registers ......................................................................................... ................. 33 4.7 top-level phase detectors................................................................................................... ........................ 34 4.7.1 pd engine ................................................................................................................. .............................. 34 4.8 top-level line timing signal reference ...................................................................................... ................ 35 4.9 top-level alarm status output signals (through gpio) ........................................................................ ..... 36 5 strong fec (reed-solomon and digital wrapper) supermacro ...................................................................... .. 37 5.1 strong fec introduction..................................................................................................... ........................... 37 5.2 functional description of strong fec........................................................................................ ................... 38 5.2.1 strong fec mode description............................................................................................... .................. 39 5.2.2 strong fec overhead and digital wrapper overhead definition ........................................................... 41 5.3 strong fec supermacro clocking domain specification ......................................................................... .... 44 5.4 alarm definition table...................................................................................................... ............................. 44 5.5 otuk overhead generation .................................................................................................... ..................... 45 5.6 strong fec alarm actions .................................................................................................... ........................ 51 5.7 overview, general functional description, and block diagram of strong fec supermacro submacros.... 52 5.7.1 elastic store (es) macro .................................................................................................. ....................... 52 5.7.2 dw macro.................................................................................................................. .............................. 52 5.7.3 reed-solomon (rs) macro ................................................................................................... .................. 52 5.7.4 scrambler/descrambler macro............................................................................................... ................. 52 5.7.5 error insert macro........................................................................................................ ............................ 53 5.7.6 framer macro .............................................................................................................. ............................ 53 5.7.7 interleaver/deinterleaver macro ........................................................................................... ................... 53 6 strong fec supermacro elastic store (transmit direction)...................................................................... ......... 54
table of contents (continued) contents page agere systems inc. 3 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 6.1 elastic store (tx) functional description ................................................................................... ................... 54 7 strong fec supermacro fec/dw framer (los, oof, lof) ........................................................................... 55 7.1 functional description of fec/dw framer..................................................................................... .............. 55 7.1.1 loss-of-signal (los) detector ............................................................................................. ................... 55 7.1.2 framer (a1 and a2)........................................................................................................ ......................... 56 7.1.3 loss-of-frame (lof) detector .............................................................................................. .................. 60 7.1.4 provisioning and alarm operation in 10 gbits/s mode........................................................................ .... 60 8 digital wrapper insert ........................................................................................................ ................................. 61 8.1 functional description of digital wrapper insert............................................................................ ............... 61 8.1.1 framing bytes insert ...................................................................................................... ......................... 62 8.1.2 internal fec overhead byte insert (oh0 to oh3) ............................................................................ ...... 63 8.1.3 bip-8 calculation......................................................................................................... ............................ 65 8.1.4 general definition of bei, bdi, and iae insert and monitor ................................................................ .... 66 8.1.5 otu section monitoring (sm) ............................................................................................... .................. 68 8.1.6 path monitoring insert (pm)............................................................................................... ...................... 72 8.1.7 pm statistics............................................................................................................. ............................... 74 8.1.8 tandem connection insert (tcmi) ........................................................................................... ............... 74 8.1.9 tcm statistics ............................................................................................................ ............................. 76 8.1.10 alarm indication signal (ais), open connection indication (oci), locked (lck), and fixed pattern insert ....................................................................................................... ................. 76 8.1.11 dwac insert.............................................................................................................. ............................ 79 8.1.12 prbs insert and monitor.................................................................................................. ..................... 80 8.1.13 digital wrapper check byte insert ........................................................................................ ................ 82 9 strong fec supermacro reed-solomon (rs) encoder............................................................................... ...... 82 9.1 functional description of rs encoder ........................................................................................ .................. 82 10 strong fec supermacro scrambler .............................................................................................. ................... 83 10.1 functional description of strong fec supermacro scrambler.................................................................. .83 11 strong fec supermacro error insert ........................................................................................... .................... 84 11.1 functional description of error insert..................................................................................... ..................... 84 12 interleaver.................................................................................................................. ....................................... 86 12.1 functional description of interleaver...................................................................................... ..................... 86 13 deinterleaver ................................................................................................................ .................................... 86 13.1 functional description of deinterleaver .................................................................................... .................. 86 14 framer receive direction requirements........................................................................................ .................. 86 15 strong fec supermacro descrambler ............................................................................................ ................. 88 15.1 functional description of descrambler ...................................................................................... ................. 88 16 reed-solomon (rs) decoder.................................................................................................... ....................... 89 16.1 functional description of rs decoder ....................................................................................... ................. 89 16.1.1 error detect and correct ................................................................................................. ...................... 89 16.1.2 ber monitor .............................................................................................................. ............................ 89 16.1.3 error count .............................................................................................................. .............................. 90 17 digital wrapper drop ......................................................................................................... ............................... 94 17.1 functional description of digital wrapper drop ............................................................................. ............. 94 17.1.1 internal fec overhead bytes monitor (oh0 to oh3) ......................................................................... .. 94 17.1.2 bip-8 monitor (see figure 32 on page 65) ................................................................................... ........ 96 17.1.3 bii monitor?bdi detect and bei monitor ................................................................................... .......... 97 17.1.4 otu section monitoring (sm) .............................................................................................. ................. 97 17.1.5 odu path monitoring (pm)................................................................................................. ................... 99 17.1.6 oduk tandem connection monitoring (tcm) .................................................................................. .. 104 17.1.7 dwac drop................................................................................................................ ......................... 106 17.1.8 insertion of ais, oci, and other fixed patterns .......................................................................... ....... 107
table of contents (continued) contents page 4 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17.1.9 prbs monitor............................................................................................................. ......................... 110 17.1.10 prbs insert............................................................................................................. .......................... 111 17.1.11 no fix stuff mode....................................................................................................... ....................... 111 18 elastic store (receive direction) ............................................................................................ ........................ 112 18.1 functional description of elastic store receive direction .................................................................. ...... 112 19 sonet fec (bch weak/in band) supermacro ...................................................................................... ...... 113 19.1 sonfec (bch weak/in band) introduction..................................................................................... ........ 113 19.2 functional description of sonet fec (bch weak/in band) supermacro.............................................. 113 19.3 sonfec ais/rdi generation .................................................................................................. ................ 115 19.3.1 sonfec (bch weak/in band) overview ....................................................................................... .... 115 19.3.2 transmit ais............................................................................................................. ........................... 115 19.3.3 receive ais.............................................................................................................. ........................... 116 19.3.4 transmit rdi generation.................................................................................................. ................... 117 19.4 sonfec interrupt structure ................................................................................................. .................... 117 20 bch macro .................................................................................................................... ................................. 118 20.1 functional description of bch macro ........................................................................................ ............... 118 20.1.1 bch encoder.............................................................................................................. ......................... 121 20.1.2 bch decoder .............................................................................................................. ........................ 124 20.1.3 bch statistics (bch-stat) ................................................................................................ ................... 125 21 sonfec input mux and output mux .............................................................................................. ............. 128 21.1 functional description of sonec input mux and output mux ............................................................... 128 22 loss-of-signal (los) detector and framer ..................................................................................... ............... 128 22.1 functional description of los detector and framer .......................................................................... ...... 128 22.1.1 loss-of-signal (los) detector ............................................................................................ ................ 128 22.1.2 framer (a1 and a2)....................................................................................................... ...................... 128 23 transmit alignment fifo...................................................................................................... .......................... 131 23.1 functional description of transmit alignment fifo .......................................................................... ....... 131 24 b1 monitoring................................................................................................................ .................................. 132 24.1 functional description of b1 monitoring .................................................................................... ............... 132 25 descrambler .................................................................................................................. ................................. 132 25.1 functional description of the descrambler .................................................................................. ............. 132 26 transpose demultiplexer...................................................................................................... .......................... 133 26.1 functional description of the transpose demultiplexer (tdmx) .............................................................. 1 33 27 rdi/ais detection............................................................................................................ ............................... 134 27.1 functional description of rdi/ais detection ................................................................................ ............ 134 28 b2 monitoring................................................................................................................ .................................. 135 28.1 functional description of b2 monitoring .................................................................................... ............... 135 29 ber?sd/sf detection .......................................................................................................... ........................ 136 29.1 functional description of ber?sd/sf detection.............................................................................. ...... 136 30 receive transport overhead processing........................................................................................ ............... 138 30.1 functional description of the receive transport overhead processing................................................... 138 30.1.1 global overhead byte processing .......................................................................................... ............ 139 31 transmit transport overhead (toh) processor .................................................................................. .......... 148 31.1 functional description of toh processor.................................................................................... ............. 148 31.1.1 global overhead byte insertion ........................................................................................... ............... 150 32 receive toac drop/transmit toac insert ....................................................................................... ............ 160 32.1 receive toac drop .......................................................................................................... ....................... 160 32.2 transmit toac insert ....................................................................................................... ........................ 160 32.3 toac modes ................................................................................................................. ........................... 161 32.3.1 full toac insert/drop mode ............................................................................................... ................ 161 32.3.2 partial toac insert/drop mode............................................................................................ ............... 161
table of contents (continued) contents page agere systems inc. 5 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 33 receive/transmit payload processing .......................................................................................... ................. 162 33.1 receive payload processing ................................................................................................. ................... 162 33.2 transmit payload processing ................................................................................................ ................... 163 34 b2 computing ................................................................................................................. ................................ 164 34.1 functional description of b2 computing..................................................................................... .............. 164 35 transpose multiplexer (tmx) .................................................................................................. ....................... 165 35.1 functional description of the tmx .......................................................................................... .................. 165 36 scrambler .................................................................................................................... ................................... 165 36.1 functional description of the scrambler in the transpose multiplexer ..................................................... 16 5 37 b1 computing ................................................................................................................. ................................ 166 37.1 functional description of b1 computing..................................................................................... .............. 166 38 microprocessor interface ..................................................................................................... ........................... 167 38.1 microprocessor interface overview.......................................................................................... ................. 167 38.2 subblock address space assignment .......................................................................................... ............ 167 38.3 microprocessor interface modes............................................................................................. .................. 168 38.4 microprocessor interface pinout descriptions............................................................................... ............ 168 38.5 reset behavior............................................................................................................. ............................. 170 38.6 microprocessor data bus width.............................................................................................. .................. 171 38.7 transfer error acknowledge (mode 1 and mode 2 only)........................................................................ .. 171 38.8 interrupt structure ........................................................................................................ ............................. 172 38.9 interrupt alarm and interrupt persistency registers ........................................................................ ......... 172 38.10 performance monitor (pm) clock............................................................................................ ................ 173 38.11 general purpose input/output (gpio)....................................................................................... ............. 174 39 tfec primary clock inputs .................................................................................................... ........................ 179 40 tfec clock multiplexers ...................................................................................................... .......................... 180 40.1 clock multiplexers and register bits selection............................................................................. ............ 180 40.2 clock selection ............................................................................................................ ............................. 180 41 tfec data multiplexers....................................................................................................... ........................... 182 41.1 data multiplexers and register bits selection .............................................................................. ............ 182 42 tfec phase detectors......................................................................................................... .......................... 183 42.1 clock division select...................................................................................................... ........................... 183 42.2 clock selection ............................................................................................................ ............................. 183 43 tfec loopbacks ............................................................................................................... ............................. 185 44 tfec valid modes............................................................................................................. ............................. 186 44.1 general conditions on primary clock inputs ................................................................................. ........... 186 45 outline diagram.............................................................................................................. ................................ 187 45.1 792-pin pbgam1th ........................................................................................................... ...................... 187 46 list of acronyms ............................................................................................................. ................................ 188 47 ordering information......................................................................................................... .............................. 203
6 6 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview the following diagrams show simplified pictures of the major blocks and i/o information of the tfec0410g device. the device has a flexible setup to allow for operation in terminal and regenerator applications. figure 1 shows the device in 2.5 gbits/s mode, and figure 2 on page 7 shows the device in 10 gbits/s mode. for convenience, two symbol sets are provided for the transmit and receive line and system interface pins, based on the mode of the device. figure 1. tfec i/o block diagram?2.5 gbits/s mode rdso_1_[3:0] rdso_2_[3:0] rdso_3_[3:0] rdso_4_[3:0] tdsi_1_[3:0] tdsi_2_[3:0] tdsi_3_[3:0] tdsi_4_[3:0] jtag interface tdo tdi tck tms trst_n microprocessor interface parity_[1:0] data_[15:0] address_[15:0] cs_n ts_n ds_n rw_n rclksi[1?4] rclkso_[1?4] pclk ta_n tea_n inth/l_n pm_clk rst_n iddq_n tclksi_[1?4] ttoac_clki_[1?4] ttoac_synco_[1?4] ttoac_data_[1?4]_[3:0] rtoac_clk_[1?4] rtoac_synco_[1?4] rtoac_data_[1?4]_[3:0] tclk_li_[1?4] t/rdw_clko_[1?4] t/rdw_synco_[1?4] t/rdw_datai/o_[1?4] tdw_deni_[1?4] tdlo_1_[3:0] tdlo_2_[3:0] tdlo_3_[3:0] tdlo_4_[3:0] tclklo_[1?4] rdli_1_[3:0] rdli_2_[3:0] rdli_3_[3:0] rdli_4_[3:0] rclkli_[1?4] line side system side phase det. x4 x4 tphase_up_[1?4] tphase_dw_[1?4] rphase_up_[1?4] rphase_dw_[1?4] 8 15 rxrefo_[1?4] tfrmli[1?4] ttoac_den_[1?4] gpio_[47?0] mpmode_as, mptype_im, mpdb_8_16, mpparen 14 8 8 phase det. 15 14 strong fec (reed-solomon) out-of-band and digital wrapper with optical channel overhead processing sts-48 system interface sts-48 section/line overhead monitor/insert bch-3 encode dwfec sonfec sts-48 line interface 8
agere systems inc. 7 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) figure 2. tfec i/o block diagram?10 gbits/s mode rdso_[15:0] sts-192 system interface tdsi_[15:0] jtag interface tdo tdi tck tms trst_n microprocessor interface parity_[1:0] data_[15:0] address_[15:0] cs_n ts_n ds_n rw_n rclksi[1] rclkso_[1] pclk ta_n tea_n inth/l_n pm_clk rst_n iddq_n tclksi_[1] ttoac_clki_[1?4] ttoac_synco_[1?4] ttoac_data_[1?4]_[3:0] rtoac_clk_[1?4] rtoac_synco_[1?4] rtoac_data_[1?4]_[3:0] tclk_li_[1] t/rdw_clko_[1?4] t/rdw_synco_[1?4] t/rdw_datai/o_[1?4] tdw_deni_[1?4] tdlo_[15:0] tclklo_[1] rdli_[15:0] rclki_[1] line side system side strong fec (reed-solomon) phase det. tphase_up_[1] tphase_dw_[1] rphase_up_[1] rphase_dw_[1] 8 rxrefo_[1] tfrmli[1] ttoac_den_[1?4] gpio_[47?0] mpmode_as, mptype_im, mpdb_8_16, mpparen 8 8 phase det. 85 79 15 14 or or 85 79 15 14 or or out-of-band and digital wrapper with optical channel overhead processing dwfec sonfec sts-192 section/line overhead monitor/insert bch-3 encode sts-192 line interface 8
8 8 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) 2.1 device modes overview the tfec0410g has several functional modes to allow for operation in terminal and regenerator applications. table 1, tfec0410g operating modes, on page 8 outlines the system and line interface rate requirements in dif- ferent applications. other combinations which may be acceptable operating modes of the device can be pro- grammed, but are not guaranteed to function error-free. note: the number in parenthesis, when present, is the effectual rate due to no stuffing. table 1. tfec0410g operating modes mode receive interface transmit interface rx?line (gbits/s) rx?system (gbits/s) tx?system (gbits/s) tx?line (gbits/s) strong fec/digital wrapper?terminal 10g 10.7 (10.66) 9.953 9.953 10.7 (10.66) quad 2.5g 2.66 2.48 2.48 2.66 gbe 11.05 10.312 10.312 11.05 strong fec/digital wrapper?regenerator 10g 10.7 (10.66) internal loopback 10.7 (10.66) quad 2.5g 2.66 internal loopback 2.66 gbe 11.05 internal loopback 11.05 strong fec or digital wrapper with strong fec?bidirectional mode 10g 10.7 (10.66) 10.7 (10.66) 10.7 (10.66) 10.7 (10.66) quad 2.5g 2.66 2.66 2.66 2.66 weak fec?terminal 10g 9.953 9.953 9.953 9.953 quad 2.5g 2.488 2.488 2.488 2.488 weak fec?regenerator 10g 9.953 internal loopback 9.953 quad 2.5g 2.488 internal loopback 2.488 strong/weak?terminal 10g 10.7 (10.66) 9.953 9.953 10.7 (10.66) quad 2.5g 2.66 2.488 2.488 2.66 strong/weak ?regenerator 10g 10.7 (10.66) internal loopback 10.7 (10.66) quad 2.5g 2.66 internal loopback 2.66 digital wrapper/weak ?terminal 10g 10.7 (10.66) 9.953 9.953 10.7 (10.66) quad 2.5g 2.66 2.488 2.488 2.66 asymmetric multiplex mode 10g ? quad 2.5g 10.7 (10.66)/9.953 2.488 2.488 10.7 (10.66)/9.953 single 2.5 gbits/s mode (16-bit line/system interface) 2.5g ? 2.5g 2.66/2.488 2.66/2.488 2.66/2.488 2.66/2.488 asymmetric: strong/digital wrapper with/without weak 10g quad 2.5g 10.7 (10.66) quad?2.488 9.953 quad?2.66 asymmetric?weak 10g quad 2.5g 9.953 quad?2.488 9.953 quad?2.488 asymmetric?tx/rx directions e.g., rx = 10g weak, tx = quad 2.5g strong 9.953 9.953 2.488 2.66
agere systems inc. 9 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) 2.2 system interface overview the system interface block has the three following modes of operation: ? one group of 16 bits at 622.08/666.51/669.32 mbits/s for a 9.953 gbits/s data rate. ? four groups of 4 bits at 622.08/666.51 mbits/s for quad 2.488 gbits/s. ? one group of 16 bits at 155.52/166.63 mbits/s. this interface allows transmit-to-receive loopback. note: the system interface can run at other rates in strong fec or digital wrapper mode. this rate is dependent on the system-side data rate, where this rate is 238/255 (14/15) or 237/255 (79/85) (10 gbits/s mode with one fixed stuff column) of the line rate. 2.3 section/line overhead insert/drop overview (figure 3) the section/line overhead blocks accept four clocks and four 32-bit data streams in quad 2.5 gbits/s mode, one clock and one 32-bit data stream in single 2.5 gbits/s mode, or one clock and one 128-bit data bus in single sts-192/stm-64 mode. serial toac channels for insert (4)/drop (4) of the transport overhead bytes are provided. the section/line overhead block (figure 3, sonet/sdh line/section overhead processing with bch-3 capability, on page 10) performs framing?normal/enhanced (oof, lof), loss-of-signal detection (los), scram- bling/descrambling, time-slot interchange (tsi) (if necessary) (sts-192/stm-64 only), alignment fifo (asymmet- ric multiplex mode only), internal monitoring/insertion of select section and line overhead bytes (j0, b1, f1, b2, k1/k2 (ais-l, rdi-l), b2, s1, m1), and fec status correction (fsi) (bch-3 processing). along with these monitor- ing/insert capabilities, the generation of ais-l under hardware or software control is provided. four ber algorithms are provided per stream (sts-48/stm-16 or sts-192/stm-64) to calculate signal fail (sf) and signal degrade (sd) conditions before and after bch-3 error correction. the b1/b2 calculation (insert) monitor, scramble/descram- ble, transpose, alignment fifo, bch-3 encoder/decoder, and section/line overhead can all be bypassed indepen- dently per function and per sts-48/sts-192 stream. a prbs generator and monitor are provided per sts-48 signal for continuity checking. this signal is placed into the sts-48 or within each sts-48 signal within a sts-192 payload with a pointer value of 522. this fixed value allows monitoring at the receiver end without the need for a pointer interpreter. note: the pointer is set by the incoming signal. only when prbs data is injected into the sonet frame is the pointer set, by the device, to 522.
10 10 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) 2.3 section/line overhead insert/drop overview (figure 3) (continued) figure 3. sonet/sdh line/section overhead processing with bch-3 capability 2.4 toac insert/drop channel overview four toac insert/drop functions are provided in quad sts-48/stm-16 mode and one function is provided in sts-192/stm-64 mode. these interfaces can operate in full toac drop/insert mode (section 2.4.1) and in partial insert/drop mode (section 2.4.2 on page 12). 2.4.1 mode 1?full toac drop/insert mode the following signals are provided per channel: ? one output clock at 20.736 mhz. ? one output sync at 8 khz coincident with the msn (most significant nibble) of the first a1 byte. ? one input enable signal (tx only) active during the msn (most significant nibble) and/or the lsn (least signif- icant nibble) of each byte that may be inserted into the output stream. there is only one control signal per stream. this is an encoded signal programmed as follows: ? 11 = insert toac data. ? 00 = default. ? 01 = pass data from incoming data stream. ? 10 = software controlled data. ? one set per sts-48/stm-16 frame input/output data bus (insert/drop?tx/rx direction, respectively)?4 bits/stream at 20.736 mbits/s that transition at the rising edge of the clock (10,368 bits per sts-48/stm-16 sonet/sdh frame). each sts-48/stm-16 within the sts-192/stm-64 stream is output independently. framer, b1 mon. dscr bch-3 decode/ correct, b2 mon section/ line term. toac drop (1.728 mbits/s or 20.736 mbits/s) b1 mon, b2 mon, j0, f1, aps, s1, rei?internal monitors system side framer, b1 mon. b2 mon toac insert (1.728 mbits/s or 20.736 mbits/s) scr (oof, lof, los) section/ line/ ais, ins. b1 calc. (oof, lof, los) b2 calc. j0, f1, aps, fsi (bch-3) k2[2:0]?rdi-l/ais-l, s1, rei?internal insert (ais ins) bch stats ber sf/sd b1 or b2 b2 prbs mon ber sf/sd prbs, prbs transmit direction receive direction t t = transpose block t t line side r x ref fsi mon b2 calc. b1 calc. a a = alignment fifo t err. ins bch-3 encode dscr scr (8 khz)
agere systems inc. 11 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) 2.4 toac insert/drop channel overview (continued) table 2 shows the byte ordering for a sts-192/stm-64 signal in sonet/sdh byte ordering, and table 3 on page 11 shows a sts-192/stm-64 in sts-48/stm-16 byte ordering. the toac channels output/accept the nibble data in sts-48/stm-16 byte order independent of the full drop/insert mode. therefore, in sts-192/stm-64 mode, four toac channels are needed to drop/insert the entire transport overhead bytes. a byte is inserted into the trans- mit data stream through an external input that is sampled per clock cycle. table 2. toac?sts-192 sonet/sdh byte ordering table 3. toac?sts-192 or sts-48 (use sts-192 numbers) in sts-48 byte ordering time (top to bottom, then left to right) ? ? sts-192 number 1 49 97 145 2 50 98 146 3 51 99 147 1 4 52 100 148 5 53 101 149 6 54 102 150 7 55 103 151 8 56 104 152 9 57 105 153 10 58 106 154 11 59 107 155 12 60 108 156 13 61 109 157 14 62 110 158 15 63 111 159 16 64 112 160 17 65 113 161 18 66 114 162 19 67 115 163 20 68 116 164 21 69 117 165 22 70 118 166 23 71 119 167 24 72 120 168 25 73 121 169 26 74 122 170 27 75 123 171 28 76 124 172 29 77 125 173 30 78 126 174 31 79 127 175 32 80 128 176 33 81 129 177 34 82 130 178 35 83 131 179 36 84 132 180 37 85 133 181 38 86 134 182 39 87 135 183 40 88 136 184 41 89 137 185 42 90 138 186 43 91 139 187 44 92 140 188 45 93 141 189 46 94 142 190 47 95 143 191 48 96 144 192 time (top to bottom, then left to right for each sts-48 channel) ? toac pins 1 13 25 37 2 14 26 38 3 15 27 39 rtoac_datao_4_[3:0] 416284051729416183042 719314382032449213345 10 22 34 46 11 23 35 47 12 24 36 48 49 61 73 85 50 62 74 86 51 63 75 87 rtoac_datao_3_[3:0] 52 64 76 88 53 65 77 89 54 66 78 90 55 67 79 91 56 68 80 92 57 69 81 93 58 70 82 94 59 71 83 95 60 72 84 96 97 109 121 133 98 110 122 134 99 111 123 135 rtoac_datao_2_[3:0] 100 112 124 136 101 113 125 137 102 114 126 138 103 115 127 139 104 116 128 140 105 117 129 141 106 118 130 142 107 119 131 143 108 120 132 144 145 157 169 181 146 158 170 182 147 159 171 183 rtoac_datao_1_[3:0] 148 160 172 184 149 161 173 185 150 162 174 186 151 163 175 187 152 164 176 188 153 165 177 189 154 166 178 190 155 167 179 191 156 168 180 192
12 12 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) 2.4 toac insert/drop channel overview (continued) 2.4.2 mode 2?partial insert/drop mode the first sts-1/stm-0 (j0, e1, d1?d3, d4?d12, s1, e2, etc.), including the m1 byte, are accessible: ? one output clock at 1.728 mhz. ? one output sync at 8 khz coincident with the msb (most significant bit) of the first a1 bit. ? one input enable signal (tx only) active during bit 7 (msb) and/or bit 6 of each byte that may be inserted into the output stream. there is only one control signal per stream. this is an encoded signal which behaves as follows: ? 11 = insert toac data. ? 00 = default. ? 01 = pass data from incoming data stream. ? 10 = software controlled data. ? one input/output data bit (insert/drop?tx/rx direction, respectively)?1 bit at 1.728 mbits/s that transitions at the rising edge of the clock (216 bits per sts-192/stm-64 or sts-48/stm-16 frame). table 4 summarizes the frame format in the sts-1/stm-0 mode. data is transmitted from left to right, then top to bottom, with a1 bit 7 being the first bit to be transmitted/received. table 4. toac insert/drop frame format?sts-1/stm-0 mode row column numbers 123 section/rs 1 a1 a2 j0 2b1e1f1 3 d1d2d3 line/ms 4 h1 h2 h3 5 b2k1k2 6 d4d5d6 7 d7d8d9 8 d10 d11 d12 9s1m1 1 1. the z2 byte is overwritten by the m1 value. e2
agere systems inc. 13 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) 2.5 in-band (weak) fec overview (bose-chaudhuri-hocquenghem (bch-3)) the weak fec operates on a quad sts-48/stm-16 and a single sts-192/stm-64 signal as per t1x1.5/99-218r2 and g.707 standards. the bit-interleaved (x8) bch-3 (4359, 4320) allows for triple error correc- tion per block. in quad sts-48/stm-16 mode, 24 consecutive bit errors can be corrected. in sts-192/stm-64 mode, 96 consecutive bit errors can be corrected because the signal is encoded on a per-sts-48/stm-16 basis. the check bit locations, per row, are fixed per the standards. the decoder allows a hardware control of the decoder/error correction logic per stream or software control of the decoder/encoder correction logic. either mode is provisionable through software. the modes are as follows: 1. hardware mode: transition between the two submodes is hitless and controlled by the fsi status bits: ?correct with data delay. ?do not correct with data delay. 2. software control (independent of fsi status): ?fec correction enabled. ?fec correction off with decoder delay. ?fec correction off without decoder delay. ?fec monitor mode without decoder delay. the raw bit error count/block count is provided to the software along with the number of uncorrectable blocks. these values are accumulated in individual saturating counters per sts-48/stm-16/sts-192/stm-64 stream. the encoder allows three modes of operation per stream entirely under software control. transition between hard- ware mode and software control is hitless. 1. fec encoder on with delay. 2. fec encoder off with delay. 3. fec encoder off without delay. the total delay through the encoder or decoder is less than 15 s each.
14 14 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) 2.6 strong fec (g.975) and digital wrapper (otn) processing overview the strong fec performs out-of-band forward error correction in quad sts-48/stm-16 mode or in single sts-192/stm-64 mode. for example, in quad sts-48/stm-16 mode, the payload rate (system interface) is 2.488 gbits/s while the line rate is 2.66 gbits/s. in single sts-192/stm-64 mode, the payload rate is 9.953 gbits/s while the line rate is 10.66 (10.7) gbits/s (stuff). any line/system rates that satisfy the 15/14 (255/238) ratio or 85/79 (255/237) are acceptable inputs for the tfec0410g device. the macro (figure 4) consists of eight elastic stores (four tx, four rx), an fec/dw frame create/monitor, an fec/dw?dwac (digital wrapper access channel) drop/insert block, an rs encoder/decoder, a scrambler/descrambler, an fec/dw framer block, a byte interleaver, and a byte deinterleaver. figure 4. digital wrapper and strong fec block diagram 2.6.1 elastic stores (es) four elastic stores per direction are provided to map/demap data to/from the fec/dw frame format. each elastic store functions independently in quad mode, while in single mode all four work together. they have no stuffing mechanism to accommodate sustained differences between the incoming and outgoing clocks. this requires the read and write clocks to be locked together using the on-board phase detector outputs (or equivalent circuitry) as inputs to external pll logic. tx es 1 tx es 2 tx es 3 tx es 4 rx es 1 rx es 2 rx es 3 rx es 4 elastic stores 4 x 78 mhz 4 x 78 mhz 128 bits 128 bits fec/dw dwac insert rs prbs ins dscr fec/dw (oof, lof, los) rs decoder rs prbs mon fec/dw overhead monitor, 4 x 83 mhz 4 x 83 mhz receive side transmit side to/from line interface err to/from sonet/sdh or system interface dwac drop ais mon/gen 10g lb lb fec/dw lb lb byte byte interleave ins/ scr encoder frame create, ais gen frame 10g deinter- leave frame stats/ber 4 x 83 mhz or
agere systems inc. 15 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) 2.6 strong fec (g.975) and digital wrapper (otn) processing overview (continued) 2.6.2 rs encoder/decoder and digital wrapper basis frame format the strong fec code used to protect the payload/overhead information against transmission errors is a reed-solomon code specified in itu-t/g.975 and g.709. the rs (255, 239) code block, shown in figure 5, is a nonbinary code and belongs to the family of systematic linear cyclic block codes. figure 5. 16-way (or 64-way) interleaved rs (255, 239) frame (fec frame) as can be seen, there is 1 overhead byte, 238 information bytes, and 16 check bytes per rs (255, 239) code block. in order to enhance the immunity of transmission system to the burst errors, 16 (or 64) rs (255, 239) code blocks are interleaved to form a fec frame. transmission order is column-by-column, i.e., after 16 (or 64) over- head bytes are transmitted, the first information byte of the second column will be transmitted. there are five different modes of operation, as shown in table 5. table 5. modes of operation fec payload type interleaving depth overhead processing quad 2488 mbits/s 16 fec frame digital wrapper (dw) frame single 9952 mbits/s 16 fec frame digital wrapper (dw) frame 64 digital wrapper (dw) frame check data framing data (1 byte) (16 bytes) information (238 bytes) payload of fec (239 bytes) code block (255 bytes) 16 (or 64) code blocks
16 16 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) 2.6 strong fec (g.975) and digital wrapper (otn) processing overview (continued) in quad 2.5 gbits/s mode, the strong fec macro processes four different 32-bit wide data streams at four different 83 mhz clocks. in 10 gbits/s mode, the strong fec macro processes a single 128-bit wide data stream at a single 83 mhz clock. 16-way or 64-way interleaving is programmable in 10 gbits/s mode, while there is only 16-way inter- leaving in quad 2.5 gbits/s mode. the tfec0410g supports the following synchronous g.709 mappings: (system interface) cbr2g5 ? opu1 ? odu1 ? otu1 (line interface) (sts-48/stm-16, atm, ip, ethernet, etc.) (system interface) cbr10g ? opu2 ? odu2 ? otu2 (line interface) (sts-192/stm-64, atm, ip, ethernet, etc.) the dw frame consists of four fec frames, and each fec frame consists of 16-way interleaving rs (255, 239) code blocks, as shown in figure 6. in 16-way interleaving (dashed arrow), the overhead columns are spaced by 4064 bytes (254 16 rows/fec frame), while in 64-way interleaving (solid arrow), all 64 overhead bytes are con- secutively transmitted and repeated after 16256 bytes (4 [254 16]). each rs block can correct up to eight sym- bol errors. therefore, with 16-way interleaving, 1024 (16 interleaving 8 symbols 8 bits/symbol) consecutive bit errors can be corrected; while in 64-way interleaving, 1024 4 = 4096 consecutive bit errors can be corrected. the number of bit or block errors and uncorrected blocks are accumulated in saturating counters per stream. this infor- mation is used as the raw input to a ber algorithm. when the strong fec is in digital wrapper mode, overhead definition and processing are different from those in fec mode. figure 6. digital wrapper?optical channel overhead (16-way/64-way interleaving) optical channel overhead bytes (64) fec frame #3 parity data (x16) (x64) (x16) oh1 oh2 oh3 oh4 fec frame #2 parity data fec frame #4 parity data fec frame #1 parity data
agere systems inc. 17 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) 2.6 strong fec (g.975) and digital wrapper (otn) processing overview (continued) 2.6.3 fec overhead and digital wrapper overhead definition the entire overhead for both fec and dw frames is programmable through the digital wrapper access channel (dwac). this allows flexibility in its definition for future changes in the standards. internally, 4 bytes can be moni- tored with continuous n-times detect (cntd) monitors. these monitors can be combined in four different configu- rations. they can be grouped as four 1-byte monitors, two 2-byte monitors, one 3-byte and one 1-byte monitor, or one 4-byte monitor. the multiple bytes do not need to be continuous. 4 bytes can be inserted from an internal reg- ister per stream. table 6 summarizes the overhead sources for each byte in the fec or dw frame. the fec overhead repeats every fec frame. the position and location of the framing bytes are provisionable from a minimum of 2 bytes to a maximum of 16 bytes in steps of 2 bytes. all other bytes that have not been assigned as framing bytes can come from the four internal registers for each 2.5 gbits/s signal or from the dwac. backward error indications (bei) and status indications (bdi) are provided on-chip. table 6. fec/digital wrapper overhead source notes: any value not from an internal register or the dwac channel is set to zero. two (three) bip-8 calculations are provided over the opuk and payload bytes only; overhead and check bits are excluded from the calculation. the calculated values can be compared against a selected overhead byte. errors are accumulated in saturating counters. a possible dw/otm-0 signal overhead format is defined in figure 7 on page 18. this format and many others are allowed and created from the internal and dwac capabilities. 12345678910111213141516 1 programmable framing bytes (location/value?internal), and others from dwac or internal registers (4 max) 2 programmable framing bytes (location/value?internal), and others from dwac or internal registers (4 max) 3 programmable framing bytes (location/value?internal), and others from dwac or internal registers (4 max) 4 programmable framing bytes (location/value?internal), and others from dwac or internal registers (4 max)
18 18 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) 2.6 strong fec (g.975) and digital wrapper (otn) processing overview (continued) note: column and row are defined as row and frame, respectively, for register definitions. figure 7. possible overhead definition for otuk signals 2.6.4 fec/dw?dwac (digital wrapper access channel) drop/insert block four insert digital wrapper access channels (dwacs) are provided on-chip along with four drop dwacs. these channels provide most of the monitoring and insert capability for the fec/dw overhead bytes. the insert dwac consists of the four following signals per channel (for a total of four dw access channels): ? one output clock at ~10.455 mhz (10 gbits/s mode and quad 2.5 gbits/s mode). ? one output superframe sync (~326.7 khz/~81.68 khz?10 gbits/s (fec/dw), ~81.68 khz/~20.42 khz?quad 2.5 gbits/s (fec/dw)) coincident with the msb (most significant bit) of the first byte in frame 0, output on the rising edge of the clock. a double-wide pulse coincident with bit 6 (2.5 gbits/s mode) or lsn (10 gbits/s mode) indicates the corresponding frame contains an mfas value of zero. ? input data: 4 bits in 10 gbits/s mode and 1 bit per stream in quad 2.5 gbits/s mode, sampled on the rising edge of the clock. ? input insert enable signal: active-high signal coincident with the msb[7]?bit[6] of the byte to insert in quad 2.5 gbits/s mode or coincident with the msn and lsn in 10 gbits/s mode. this is an encoded signal set as follows: ? 11 = insert dwac data ? 00 = default ? 10 or 01 = pass data from incoming data stream. the drop dwac consists of the following three signals per channel (total of four dw access channels): ? one output clock at ~10.455 mhz (10 gbits/s mode and quad 2.5 gbits/s mode). ? one output superframe sync (~326.7 khz/~81.68 khz?10 gbits/s (fec/dw), ~81.68 khz/~20.42 khz?quad 2.5 gbits/s (fec/dw)) coincident with the msb (most significant bit) of the first byte in frame 0, output on the rising edge of the dwac clock. ? output data: 4 bits in 10 gbits/s mode and 1 bit per stream in quad 2.5 gbits/s mode, samples on the rising edge of the dwac clock. otuk fec (4 x 256 bytes) otuk payload (4 x 3808 bytes) otuk overhead column row 0 2 1 3 0 15 16 3823 4079 0 1 2 3 01234567 8910 fas mfas sm gcc0 gcc1 aps/pcc res pt 11 12 13 14 15 fec frame # gcc2 res mapping specific res act tcm6 tcm5 tcm4 ftfl tcm3 tcm2 tcm1 pm exp row #
agere systems inc. 19 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) 2.6 strong fec (g.975) and digital wrapper (otn) processing overview (continued) the data stream format to/from the device is shown in figure 8. figure 8. dwac frame definition 2.6.5 receive/transmit fec/dw framer an alpha/delta framer is provided to find the fec/dw overhead framing pattern. the following parameters of the framer are programmable through software: ? number of framing pairs. ? framing values (oa1/oa2). ? number of bytes examined to go in-frame. ? number of bytes examined to go out-of-frame. ? number of consecutive error-free framing patterns to declare in-frame. ? number of consecutive errored framing patterns to declare out-of-frame. the framer will detect a loss-of-frame (lof) state and lof parameters are programmable (number of frames to declare and number of frames to clear). under software or hardware control, an ais signal will be generated (all-ones pattern in all overhead except the framing bytes). data is optionally descrambled (rx side only) using one of the two possible polynomials (x 7 +x+1 or x 16 +x 12 +x 3 + x + 1) under user control. 2.7 line interface?mux/demux overview the line mux/demux allows the three following modes of operation: ? one group of 16 bits at 622.08/666.51/669.32 mbits/s?10 gbits/s mode ? one group of 16 bits at 155/166 mbits/s?single 2.5 gbits/s mode ? four groups of 4 bits at 622.08/666.51?quad 2.5 gbits/s mode. all modes support forward clocking only. these blocks perform parallel-to-parallel conversions from 128 bits ? 16 bits, 32 bits ? 16 bits, or 32 bits ? 4 bits, respectively. facility loopback and terminal loopback capabilities are provided at this interface for diagnostic purposes. this interface can run at other clock rates as long as the 15/14 (255/237) ratio between the system clock and line clock is maintained. [7:0] data enable sync oh1 oh2 oh3 oh4 oh5 oh6 oh7 oh8 oh9 oh10 oh11 oh12 oh13 oh14 oh15 oh16 transmitted serially or nibble wide
20 20 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) 2.8 alarm status output signals overview the status of the internal loc, oof, lof, and los monitors per 2.5 gbits/s slice are accessible on eight external transmit and eight external receive pins (16 total?gpio[15:0]). the specified alarm output on each pin is program- mable under software control. these outputs allow automatic actions to occur during certain failure conditions. (see the tfec0410g 2.5/10 gbits/s optical networking interface with strong/weak fec and digital wrapper hardware register map document for more information.) 2.9 microprocessor interface overview the tfec0410g microprocessor interface architecture is configured for glueless interface to the motorola ? mpc860 and mc68360 microprocessors. the intel ? microcontrollers 8xc251 and 80c196 and the i960 micropro- cessor may also be utilized to interface to the tfec0410g. however, provisions on the board need to be made to (de)multiplex the address and data bus. the state of the mptype_im input signal indicates to the device whether it interfaces to a motorola microprocessor or an intel microcontroller. other microprocessors may be used if their timing requirements fit to one of the modes described. the tfec0410g has separate 16-bit wide address and data busses. the mpdb_8_16 input distinguishes between an 8-bit or 16-bit wide microprocessor data bus being used. in case of an 8-bit wide microprocessor data bus interface, the eight upper bits of the device data bus ports are not being used and are held 3-state. the micro- processor interface operates at the frequency of the microprocessor clock (pclk) input which should be in the range of 10 mhz to 100 mhz. all internal counters are latched using an external or internal pm latch pulse that must occur once per second (pro- grammable) to ensure all internal counters do not saturate. 2.9.1 transfer error acknowledge (tea_n) (with mpc860 and mc68360 only) the tfec0410g contains a bus time-out counter. when this counter saturates, a bus error is generated to the external processor through the transfer error acknowledge (tea_n) signal. this feature must be considered with respect to the external ability of the processor to generate its own internal bus time-out. tea_n will be asserted if an internal data acknowledgment is not received within 32 pclk periods. this interval is used since all valid inter- nal accesses to the device will be completed in significantly less than 32 pclk periods. tea_n is also asserted if the calculated parity value does not match the parity generated by the external micropro- cessor on a data transfer. 2.9.2 interrupt structure the interrupt structure of the tfec0410g minimizes the effort for software/firmware to isolate the interrupt source. the interrupt structure is comprised of different registers depending on the consolidation level. at the lowest level (source level), there are two registers. the first is an alarm register (ar). an alarm register is typically of the write 1 clear (w1c) type. the second is an interrupt mask (im) register of the read/write (r/w) type. an alarm register latches a raw status alarm. this latched alarm may contribute to an interrupt if its corresponding interrupt mask bit is disabled. individual latched alarms are consolidated into an interrupt status register (isr). if any of the latched alarms that are consolidated into a bit of an isr are set and unmasked, the isr bit is set. the isr bit may contribute to an interrupt if its corresponding interrupt mask bit is disabled. isrs may be consolidated into a higher-level isr in a similar fashion until all alarms are consolidated into the chip-level isr. the alarm regis- ter that causes an interrupt can be determined by traversing the tree of isrs, starting at the chip-level isr, until the source alarm is found. note: interrupts are disabled when the corresponding bit in the mask register is 0. if the mask register bit is 1, the interrupt is enabled. two levels of alarms are provided: a high-interrupt output and a low-interrupt output from the device.
agere systems inc. 21 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) 2.10 clocking overview the following diagrams show simplified pictures of the major clock domains within the tfec0410g in quad 2.5 gbits/s and 10 gbits/s strong/digital wrapper/weak sonet/sdh mode. in 10 gbits/s mode, each block has one clock domain for a total of four transmission clocks along with one microprocessor clock. note: there are a total of 16 different transmission clocks and 1 microprocessor clock. figure 9. quad 2.5 gbits/s clocking overview?terminal mode rdso_1_[3:0] rdso_2_[3:0] rdso_3_[3:0] rdso_4_[3:0] tdsi_1_[3:0] tdsi_2_[3:0] tdsi_3_[3:0] tdsi_4_[3:0] up rclksi[1?4] rclkso_[1?4] pclk tclksi_[1?4] ttoac_clki_[1?4] ttoac_synco_[1?4] ttoac_data_[1?4]_[3:0] rtoac_clk_[1?4] rtoac_synco_[1?4] rtoac_data_[1?4]_[3:0] tclk_li_[1?4] tdw_clko_[1?4] tdw_synco_[1?4] tdw_datai_[1?4] tdw_deni_[1?4] tdlo_1_[3:0] tdlo_2_[3:0] tdlo_3_[3:0] tdlo_4_[3:0] tclklo_[1?4] rdli_1_[3:0] rdli_2_[3:0] rdli_3_[3:0] rdli_4_[3:0] rclkli_[1?4] line side system side phase det. phase det. tphase_up_[1?4] tphase_dw_[1?4] rphase_up_[1?4] rphase_dw_[1?4] 8 15 14 15 14 8 rxrefo_[1?4] tfrmli[1?4] ttoac_den_[1?4] tx system interface tx sonet/sdh/bch es es rx system interface fec/dw (rs) line interface rdw_clko_[1?4] rdw_synco_[1?4] rdw_datao_[1?4] 4 8 4 4 8 rx sonet/sdh/bch 4
22 22 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 device overview (continued) 2.10 clocking overview (continued) note: there are a total of 4 different transmission clocks and 1 microprocessor clock. figure 10. 10 gbits/s clocking overview?terminal mode rdso_[15:0] tdsi_[15:0] up rclksi_[1] rclkso_[1] pclk tclksi_[1] ttoac_clki_[1?4] ttoac_synco_[1?4] ttoac_data_[1?4]_[3:0] rtoac_clk_[1?4] rtoac_synco_[1?4] rtoac_data_[1?4]_[3:0] tclk_li_[1] tdw_clko_[1?4] tdw_synco_[1?4] tdw_datai_[1?4] tdw_deni_[1?4] tdlo_[15:0] tclklo_[1] rdli_[15:0] rclkli_[1] line side system side 8 8 rxrefo_[1] tfrmli_[1] ttoac_den_[1?4] tx system interface tx sonet/sdh/bch es es rx system interface fec/dw (rs) line interface rdw_clko_[1?4] rdw_synco_[1?4] rdw_datao_[1?4] 8 8 rx sonet/sdh/bch phase det. rphase_up_[1] rphase_dw_[1] 15 85 or 14 79 or tphase_up_[1] tphase_dw_[1] phase det. 15 85 or 14 79 or
agere systems inc. 23 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 3 block diagrams figure 11. tfec0410g block diagram figure 12. strong fec application: terminal bch-3 sonet/ rx sonet/ sdh bch sonet/ sonet/sdh microprocessor interface and control otn oh/ otn oh otn stats digital wrapper och/strong fec rs rs decode and correct fec/dw rs interleave 10.7 (9.953) gbits/s or quad 2.66 (2.488) gbits/s 10.7 (9.953) gbits/s or quad 2.66 (2.488) gbits/s 9.953 (10.7) gbits/s or quad 2.488 (2.66) gbits/s 9.953 (10.7) gbits/s or quad 2.488 (2.66) gbits/s framer decode/ correct bch stats monitor encoder frame insert with optical channel/frame overhead processing with weak fec (bch-3 in-band) tx sdh bch oh insert framer and de-int sonet/ sdh framer stats sdh section/ line monitoring system side line side (rs out-of-band) fec rs framer decode and correct rs stats microprocessor interface and control and de-int interleave rs encoder 10.7 gbits/s or quad 2.66 gbits/s 10.7 gbits/s or quad 2.66 gbits/s 9.953 gbits/s or quad 2.488 gbits/s 9.953 gbits/s or quad 2.488 gbits/s sonet/sdh with weak fec (bch-3 in-band) oh/ oh frame stats monitor frame insert strong fec with frame overhead processing (rs out-of-band)
24 24 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 3 block diagrams (continued) figure 13. strong fec application: regenerator (sonet/sdh section monitoring possible) figure 14. digital wrapper (och) application: otn adapter rx sonet/ sdh sonet/ sonet/sdh microprocessor interface and control rs rs decode and correct fec rs interleave 10.7 gbits/s or quad 2.66 gbits/s 10.7 gbits/s or quad 2.66 gbits/s framer stats encoder with weak fec (bch-3 in-band) framer and de-int sdh section/ line monitoring oh frame stats monitor oh/ frame insert strong fec with frame overhead processing (rs out-of-band) dw rs framer decode and correct rs stats microprocessor interface and control and de-int interleave rs encoder otn oh otn stats monitor otn oh/ frame insert 9.953 gbits/s or quad 2.488 gbits/s 9.953 gbits/s or quad 2.488 gbits/s sonet/sdh with weak fec (bch-3 in-band) 10.7 gbits/s or quad 2.66 gbits/s 10.7 gbits/s or quad 2.66 gbits/s digital wrapper och with optical channel overhead processing (rs out-of-band)
agere systems inc. 25 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 3 block diagrams (continued) figure 15. digital wrapper (och) application: otn regenerator figure 16. strong fec or digital wrapper (och) with strong fec: bidirectional mode figure 17. weak fec application: sonet/sdh terminal dw rs framer decode and correct rs stats microprocessor interface and control and de-int interleave rs encoder otn oh otn stats monitor otn oh/ frame insert sonet/sdh with weak fec 10.7 gbits/s or quad 2.66 gbits/s 10.7 gbits/s or quad 2.66 gbits/s 9.953 gbits/s or quad 2.488 gbits/s 10.7 gbits/s or quad 2.66 gbits/s or digital wrapper och with optical channel overhead processing (rs out-of-band) fec/dw rs framer decode and correct rs stats microprocessor interface and control and de-int interleave rs encoder otn oh otn stats monitor framer and frame sonet/sdh with weak fec (bch-3 in-band) 10.7 gbits/s or quad 2.66 gbits/s 10.7 gbits/s or quad 2.66 gbits/s 10.7 gbits/s or quad 2.66 gbits/s insert digital wrapper och/strong fec with optical channel/frame overhead processing (rs out-of-band) 10.7 gbits/s or quad 2.66 gbits/s bch-3 sonet/ rx sonet/ sdh bch sonet/ sonet/sdh microprocessor interface and control 9.953 gbits/s or quad 2.488 gbits/s 9.953 gbits/s or quad 2.488 gbits/s 9.953 gbits/s or quad 2.488 gbits/s framer decode/ correct bch with weak fec (bch-3 in-band) tx sdh bch oh insert sonet/ sdh framer stats sdh section/ line monitoring 9.953 gbits/s or quad 2.488 gbits/s digital wrapper och/strong fec with optical channel/frame overhead processing (rs out-of-band)
26 26 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 3 block diagrams (continued) figure 18. weak fec application: sonet/sdh regenerator figure 19. strong/weak fec application: sonet/sdh terminal bch-3 sonet/ rx sonet/ sdh bch sonet/ sdh sonet/sdh microprocessor interface and control 9.953 gbits/s or quad 2.488 gbits/s 9.953 gbits/s or quad 2.488 gbits/s 9.953 gbits/s or quad 2.488 gbits/s framer decode/ correct bch section/line monitoring with weak fec (bch-3 in-band) tx sdh bch oh insert sonet/ sdh framer stats digital wrapper och/strong fec with optical channel/frame overhead processing (rs out-of-band) bch-3 sonet/ rx sonet/ sdh bch sonet/ sdh sonet/sdh microprocessor interface and control rs rs decode and correct fec rs interleave 10.7 gbits/s or quad 2.66 gbits/s 10.7 gbits/s or quad 2.66 gbits/s 9.953 gbits/s or quad 2.488 gbits/s 9.953 gbits/s or quad 2.488 gbits/s framer decode/ correct bch section/ stats encoder with weak fec (bch-3 in-band) tx sdh bch oh insert framer and de-int sonet/ sdh framer stats line monitoring oh frame stats monitor oh/ insert frame strong fec with frame overhead processing (rs out-of-band)
agere systems inc. 27 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 3 block diagrams (continued) figure 20. strong/weak fec application: sonet/sdh regenerator figure 21. digital wrapper (och)/weak fec: otn with sonet/sdh termination bch-3 sonet/ rx sonet/ sdh bch sonet/ sdh sonet/sdh microprocessor interface and control rs rs decode and correct fec rs interleave 10.7 gbits/s or quad 2.66 gbits/s 10.7 gbits/s or quad 2.66 gbits/s framer decode/ correct bch section/ stats encoder with weak fec (bch-3 in-band) tx sdh bch oh insert framer and de-int sonet/ sdh framer stats line monitoring 9.953 gbits/s or quad 2.488 gbits/s oh frame stats monitor frame oh/ insert strong fec with frame overhead processing (rs out-of-band) bch-3 sonet/ rx sonet/ sdh bch sonet/ sdh sonet/sdh microprocessor interface and control otn oh/ otn oh otn stats rs rs decode and correct dw rs interleave 10.7 gbits/s or quad 2.66 gbits/s 10.7 gbits/s or quad 2.66 gbits/s 9.953 gbits/s or quad 2.488 gbits/s 9.953 gbits/s or quad 2.488 gbits/s framer decode/ correct bch section/ stats monitor encoder frame insert with weak fec (bch-3 in-band) tx sdh bch oh insert framer and de-int sonet/ sdh framer stats line monitoring digital wrapper och with optical channel overhead processing (rs out-of-band)
28 28 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 3 block diagrams (continued) figure 22. asymmetric multiplex mode: sonet/sdh terminal with/without strong/weak fec figure 23. single 2.5 gbits/s mode: sonet/sdh, terminal/regenerator, with strong or weak fec bch-3 sonet/ rx sonet/ sdh bch sonet/ sdh sonet/sdh microprocessor interface and control otn oh/ otn oh otn stats rs rs decode and correct fec/dw rs interleave 10.7 gbits/s or 9.953 gbits/s 10.7 gbits/s or 9.953 gbits/s quad 2.488 gbits/s quad 2.488 gbits/s framer decode/ correct bch section/ stats monitor encoder frame insert with weak fec (bch-3 in-band) tx sdh bch oh insert framer and de-int sonet/ sdh framer stats line monitoring digital wrapper och/strong fec with optical channel/frame overhead processing (rs out-of-band) bch-3 sonet/ rx sonet/ sdh bch sonet/ sdh sonet/sdh microprocessor interface and control otn oh/ otn oh otn stats rs rs decode and correct fec/dw rs interleave single 2.488/2.66 gbits/s framer decode/ correct bch section/ stats monitor encoder frame insert with weak fec (bch-3 in-band) tx sdh bch oh insert framer and de-int sonet/ sdh framer stats (16 bits) single 2.488/2.66 gbits/s (16 bits) single 2.488/2.66 gbits/s (16 bits) single 2.488/2.66 gbits/s (16 bits) line monitoring digital wrapper och/strong fec with optical channel/frame overhead processing (rs out-of-band)
agere systems inc. 29 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 4 top-level overview 4.1 top-level functionality the top-level block outlines the following functionality in detail: top-level clock and data muxes (section 4.2). loss-of-clock detectors (loc) (section 4.3 on page 31). reset architecture (hardware/software) (section 4.4 on page 32). loopback controls (section 4.5 on page 33). powerdown control functionality (section 4.6 on page 33). phase detectors (section 4.7 on page 34). line timing reference signal generation (section 4.8 on page 35). alarm status output signals through gpio pins (section 4.9 on page 36). 4.2 top-level clocking figure 24, top-level clock and datapath overview (1 of 4 slices), on page 30 shows a detailed picture of the major clock domains and datapaths within the tfec0410g in quad 2.5 gbits/s strong/digital wrapper/weak sonet/sdh mode. in 10 gbits/s mode, each block only has one clock domain for a total of four transmission clocks in addition to one microprocessor clock.
agere systems inc. 30 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 4 top-level overview (continued) 4.2 top-level clocking (continued) figure 24. top-level clock and datapath overview (1 of 4 slices) receive sts-192 system interface rdso_[1?4]_[3:0] transmit sts-192 system interface tdsi_[1?4]_[3:0] rclksi[1?4] rclkso_[1?4] tclksi_[1?4] es tclkli_[1?4] tdlo_[1-4]_[3:0] tclklo_[1--4] rdli_[1-4]_[3:0] rclkli_[1?4] i/f line tx i/f line rx line side system side 8 8 frm scr bch-enc frm dw rs-enc b/b scr frm bch-dec es frm dw rs-dec b/b r2tf_lb trsen2rrsde_lb tline2rline_lb rsys2tsys_lb t2rf_lb sys_rxclk line_txclk sys_txclk line_rxclk sys_rx78clk sys_tx78clk sys_tx78clk line_rx83clk sys_rx78clk line_tx83clk dwfec-supermacro sonfec-supermacro (a) (c) (d) (e) (f) (g) (h) (j) 8 8 (k) (l) (m) (n) (o) (p) (1) (2) (4) (5) (6) (7) (8) (10) (12) (15) (13) (18) (11) (16) (19) (21) (22) (23) (24) (14) (20) (b) (3) (i) (9) tdw2rdw_lb rdw2tdw_lb res2tes_lb clock multiplexers: (a) line_tx_hs_clkmux (b) line_tx_ls_clkmux (c) line_tx_dwfec_clkmux (d) sys_tx_dwfec_clkmux (e) sys_tx_sonfec_clkmux (f) line_rx_dwfec_clkmux (g) sys_rx_dwfec_clkmux (h) sys_rx_sonfec_clkmux (i) sys_rx_ls_clkmux (j) sys_rx_hs_clkmux data multiplexers: (k) line_tx_dmux (l) dwfec_tx_dmux (m) sonfec_tx_dmux (n) sonfec_rx_dmux (o) sonfec_rx_byp_dmux (p) sys_rx_dmux clock signals: (1) line_tx_hsclk (2) line_tx_lsclk (3) line_tx83clk (4) dwfec_tx78clk (5) sonfec_tx78clk (6) line_rx83clk (7) dwfec_rx78clk (8) sys_rx78clk (9) sys_rx_lsclk (10) sys_rx_hsclk data signals: (11) line_txdatao[127:0] (12) sonfec_txdatao[127:0] (13) dwfec_txdatao[127:0] (14) dwfec_txdatai[127:0] (15) sys_txdatai[127:0] (16) sonfec_txdatai[127:0] (18) line_rxdatai[127:0] (19) dwfec_rxdatao[127:0] (20) sonfec_rxdatai[127:0] (21) dwfec_rx83data[127:0] (22) sonfec_rxbypdata[127:0] (23) sonfec_rxdatao[127:0] (24) sys_rxdatao[127:0]
agere systems inc. 31 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 4 top-level overview (continued) 4.3 top-level loss-of-clock detectors all high-speed input clocks have loss-of-clock (loc) detectors. these detectors use the microprocessor clock as a reference and will not declare loc if the mpu clock is lost. these detectors check for activity on the monitored sig- nal. if the mpu clock is lost, the detectors will clear their loc state and will not activate the respective loc indica- tor until the mpu clock recovers. table 7. loss of clock registers function register name (first occurrence) register bits qty. 1 1. qty. refers to the number of registers that are similar to the one shown in the table. there may be more registers to control different channels, or several registers of similar type used for a particular function. 1st addr 2 (hex) 2. 1st addr (hex) refers to the address (in hex) of the first occurrence of this type of register. loc interrupt alarm dev_loc_alarm_s0 (w1c) dev_loc_line_txclk_a 4 014 dev_loc_line_rxclk_a 4 014 dev_loc_sys_txclk_a 4 014 dev_loc_sys_rxclk_a 4 014 loc alarm mask dev_loc_mask_s0 (r/w) dev_loc_line_txclk_m 4 043 dev_loc_line_rxclk_m 4 043 dev_loc_sys_txclk_m 4 043 dev_loc_sys_rxclk_m 4 043 loc persistency dev_loc_persist_s0 (ro) dev_loc_line_txclk_p 4 070 dev_loc_line_rxclk_p 4 070 dev_loc_sys_txclk_p 4 070 dev_loc_sys_rxclk_p 4 070 loc state dev_loc_state_s0 (ro) dev_loc_line_txclk 4 090 dev_loc_line_rxclk 4 090 dev_loc_sys_txclk 4 090 dev_loc_sys_rxclk 4 090
32 32 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 4 top-level overview (continued) 4.4 top-level reset architecture (hardware/software) all slices are reset when the external reset signal is asserted. the device will not exit the reset state until a clock is provided to the macro block. the reset monitor registers indicate the reset status of each block. the datapath of each slice can be individually reset through a software register. in 10 gbits/s mode, all slice resets must be written. the mpu blocks within the sonfec supermacro and the dwfec supermacro can be reset independently through software control. table 8. software reset registers function register name (first occurrence) register bits qty. 1st addr (hex) mpu reset dev_mpureg_swrst (r/w) dev_dwfec_mpu_swrst 1 0300 dev_sonfec_mpu_swrst 1 0300 dev_mpu_reg_swrst 1 0300 datapath reset dev_dp_swrst_s0 (r/w) dev_dwfec_dat_swrst 4 0301 dev_sonfec_dat_swrst 4 0301 dwfec reset monitor dwfec_rst_mon (ro) dwfec_rx_rst_mon_s3 1 02001 dwfec_rx_rst_mon_s2 1 02001 dwfec_rx_rst_mon_s1 1 02001 dwfec_rx_rst_mon_s0 1 02001 dwfec_tx_rst_mon_s3 1 02001 dwfec_tx_rst_mon_s2 1 02001 dwfec_tx_rst_mon_s1 1 02001 dwfec_tx_rst_mon_s0 1 02001 sonfec reset monitor sonfec_rst_mon (ro) rx_rst_mon_s3 1 01001 rx_rst_mon_s2 1 01001 rx_rst_mon_s1 1 01001 rx_rst_mon_s0 1 01001 tx_rst_mon_s3 1 01001 tx_rst_mon_s2 1 01001 tx_rst_mon_s1 1 01001 tx_rst_mon_s0 1 01001
agere systems inc. 33 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 4 top-level overview (continued) 4.5 top-level loopback control signals all loopback control signals are generated from the top mpu block (see section 38, microprocessor interface, on page 167 for more details). some loopback configurations are controlled by the internal data muxes. table 9. loopback control signals 4.6 top-level powerup control registers the device allows the powerup of all lvds and 3-statable input/output buffers on a per 2.5 gbits/s basis through software control registers. the mpu clock to the sonfec and dwfec blocks can be inhibited. all i/o and trans- mission paths are in the powerdown state upon hardware and mpu software resets. table 10. powerup control registers function register name (first occurrence) register bits qty. 1st addr (hex) loopback control dev_ctl_lpbk_s0 (r/w) dev_rsys2tsys_lb 4 0b0 dev_tline2rline_lb 4 0b0 dev_rdw2tdw_lb 4 0b0 dev_tdw2rdw_lb 4 0b0 dev_trsen2rrsde_lb 4 0b0 function register name (first occurrence) register bits qty. 1st addr (hex) clock inputs dev_pdn_clkin_s0 (r/w) dev_rclksi_pdn 4 0160 dev_rclkli_pdn 4 0160 dev_tclkli_pdn 4 0160 dev_tclksi_pdn 4 0160 data and frame inputs dev_pdn_in_s0 (r/w) dev_tfrmli_pdn 4 0164 dev_tdsi_pdn 4 0164 dev_rdli_pdn 4 0164 output data dev_pdn_out_s0 (r/w) dev_tclklo_pdn 4 0168 dev_tdlo_pdn 4 0168 dev_rclkso_pdn 4 0168 dev_rdso_pdn 4 0168 toac clock/sync/data dev_pdn_toaco_s0 (r/w) dev_ttoac_pdn 4 016d dev_rtoac_cs_pdn 4 016d dev_rtoac_dat_pdn 4 016d dwac clock/sync/data dev_pdn_dwaco_s0 (r/w) dev_rdw_cs_pdn 4 0171 dev_rdw_dato_pdn 4 0171 dev_tdw_cs_pdn 4 0171 sonfec/dwfec mpu powerup dev_pdn_iclk (r/w) dev_dwfec_pclk_pdn 1 016c dev_sonfec_pclk_pdn 1 016c
34 34 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 4 top-level overview (continued) 4.7 top-level phase detectors the internal phase detector generates pump_up and pump_dn signals for locking the tx 666/669 mhz line clock to the tx 622 mhz system clock with external elements such as vco and lpf (locking the rx 622 mhz sys- tem clock to the rx 666/669 mhz line clock). for various applications, reference clock (ref_clk) and variable clock (var_clk) can be selected out of any four clocks: tclkli, tclksi, rclkli, and rclksi. output polarity (pump_up, pump_dn) can be controlled by software. 4.7.1 pd engine the flip-flop based phase detector (pd) of the tfec is used to detect the phase difference. the pd?s detecting range is ?2pi ~ +2pi. in its initial state, both flip-flops are cleared by resetn, which is active-low. if ref_phs is leading var_phs, then the up pulse is output until var_phs?s rising edge is received. this will result in making var_clk faster. if ref_phs is lagging var_phs, then the down pulse is output until var_phs?s rising edge is received. this will result in making var_clk slower. a timing diagram is shown in figure 25. figure 25. timing diagram of phase detector table 11. phase detector control registers function register name (first occurrence) register bits qty. 1st addr (hex) phase detector receive direction control registers dev_ctl_rx_phdet_s0 (r/w) dev_phdet_rx_pol 4 0cc dev_phdet_rx_vardiv 4 0cc dev_phdet_rx_refdiv 4 0cc dev_phdet_rx_varsel 4 0cc dev_phdet_rx_refsel 4 0cc phase detector transmit direction control registers dev_ctl_tx_phdet_s0 (r/w) dev_phdet_tx_pol 4 0d0 dev_phdet_tx_vardiv 4 0d0 dev_phdet_tx_refdiv 4 0d0 dev_phdet_tx_varsel 4 0d0 dev_phdet_tx_refsel 4 0d0 ref_phs var_phs up dn
agere systems inc. 35 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 4 top-level overview (continued) 4.8 top-level line timing signal reference one external pin per 2.5 gbits/s interface is provided for line timing reference purposes (rxrefo[4?1]). the source of these outputs is user controllable. the choices are summarized as follows: free-running 50% duty cycle at 8 khz sync (toggle output after 4860 clock cycles) derived from the rclkli[4?1] input clocks. free-running 50% duty cycle at 8 khz sync (toggle output after 5207 clock cycles) derived from the rclksi[4?1] input clocks. the reference signals are 8 khz only with 622/666/669 mhz input clocks. table 12. line timing reference select register function register name (first occurrence) register bits qty. 1st addr (hex) line timing reference dev_ltim_ref_sel_s0 (r/w) dev_ltim_ref_sel 4 0dc
36 36 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 4 top-level overview (continued) 4.9 top-level alarm status output signals (through gpio) sixteen signals are provided, one per 2.5 gbits/s interface per transmit and receive direction accessible through the gpio[15:0] signals. the output of these signals is the oring of the following alarms with their associated inhibit bits. the equations are summarized as follow: rx_dw_alm[4?1] = dev_loc_line_rxclk and not dev_dwfec_rx_loc_inh or frm_rxlos and not dev_dwfec_rx_los_inh or frm_rxoof and not dev_dwfec_rx_oof_inh or frm_rxlof and not dev_dwfec_rx_lof_inh rx_son_alm[4?1] = dev_loc_sys_rxclk and not dev_sonfec_rx_loc_inh or rx_los and not dev_sonfec_rx_los_inh or rx_sef and not dev_sonfec_rx_oof_inh or rx_lof and not dev_sonfec_rx_lof_inh tx_dw_alm[4?1] = dev_loc_line_txclk and not dev_dwfec_tx_loc_inh or frm_txlos and not dev_dwfec_tx_los_inh or frm_txoof and not dev_dwfec_tx_oof_inh or frm_txlof and not dev_dwfec_tx_lof_inh tx_son_alm[4?1] = dev_loc_sys_txclk and not dev_sonfec_tx_loc_inh or tx_los and not dev_sonfec_tx_los_inh or tx_sef and not dev_sonfec_tx_oof_inh or tx_lof and not dev_sonfec_tx_lof_inh table 13. receive/transmit alarm inhibit registers function register name (first occurrence) register bits qty. 1st addr (hex) receive direction alarm inhibit registers dev_rx_alrmstat_inh_s0 (r/w) dev_dwfec_rx_los_inh 4 0d4 dev_dwfec_rx_lof_inh 4 0d4 dev_dwfec_rx_oof_inh 4 0d4 dev_dwfec_rx_loc_inh 4 0d4 dev_sonfec_rx_los_inh 4 0d4 dev_sonfec_rx_lof_inh 4 0d4 dev_sonfec_rx_oof_inh 4 0d4 dev_sonfec_rx_loc_inh 4 0d4 transmit direction alarm inhibit registers dev_tx_alrmstat_inh_s0 (r/w) dev_dwfec_tx_los_inh 4 0d8 dev_dwfec_tx_lof_inh 4 0d8 dev_dwfec_tx_oof_inh 4 0d8 dev_dwfec_tx_loc_inh 4 0d8 dev_sonfec_tx_los_inh 4 0d8 dev_sonfec_tx_lof_inh 4 0d8 dev_sonfec_tx_oof_inh 4 0d8 dev_sonfec_tx_loc_inh 4 0d8
agere systems inc. 37 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 5 strong fec (reed-solomon and digital wrapper) supermacro 5.1 strong fec introduction this section provides the functional description of the strong fec supermacro core: out-of-band. the functional description includes requirements that must be met, as derived from various specifications. the strong fec super- macro core consists of the following: elastic store (78 mhz ? 83 mhz) [es] macro. digital wrapper with optical channel overhead processing [dw] macro. reed-solomon (rs) macro. fec/dw framer (frm) macro. prbs insert and monitor (prbs) macro. byte interleave and deinterleave (intlv) macro. this section contains the specifications and requirements for strong forward error correction (fec).
agere systems inc. 38 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.2 functional description of strong fec the structure of strong fec supermacro is shown in figure 26. figure 26. strong fec supermacro es_dw_txdata[127:0] sys_tx78clk[3:0] wrapper digital with optical channel overhead processing top_dwac_txdata[3:0] dwfec_dwac_txsync[3:0] dwfec_dwac_txclko[3:0] top_dwac_txdata_en[3:0] line side system side sonfec_dwfec_txdata[127:0] sys_tx78rstn[3:0] es(tx) es_dw_txsync[3:0] dw (tx) prbs(tx) prbs dw_rs_txdata[127:0] dw_rs_txsync[3:0] rs(tx) reed- scrambler rs_intlv_txdata[127:0] error dwfec_line_txdata[127:0] frm(rx) fec/dw line_dwfec_rxdata[127:0] descrambler rs(rx) frm_rs_rxdata[127:0] frm_rs_rxsync[3:0] ais decoder error error correct detect ber error counter ais alarm condition wrapper digital with optical channel overhead processing dw (rx) dwfec_dwac_rxsync[3:0] dwfec_dwac_rxdata[3:0] dwfec_dwac_rxclko[3:0] prbs (rx) prbs mon & ins es(rx) elastic ais dw_es_rxdata_en[3:0] dw_es_rxsync[3:0] dw_es_rxdata[127:0] dwfec_sonfec_rxdata[127:0] rs_dw_rxdata[127:0] rs_dw_rxsync[3:0] sys_rx78clk[3:0] sys_rx78rstn[3:0] line_tx83clk[3:0] line_tx83rstn[3:0] line_rx83clk[3:0] line_rx83rstn[3:0] line_tx83frmi[3:0] bit/byte interleave insert byte deinterleave intlv (tx) intlv (rx) monitor (pm_clk) failure condition (oof/lof/los/loc) rs_intlv_txsync[3:0] line_rx83erstn[3:0] fec/dw framer frm_dw_ frm_dw_txsync[3:0] dwfec_sys_rx83data[127:0] frm(tx) line_rx83loc[3:0] dwfec_rx83oof[3:0] dwfec_rx83lof[3:0] dwfec_rx83los[3:0] sys_tx78erstn[3:0] mpu_dwfec_dw_t2r_lb mpu_dwfec_dw_r2t_lb mpu_dwfec_es_r2t_lb mpu_dw_rx_es_sys[3:0] bdi/bei (rx to tx) prbs spif dwfec mpu meta line_tx83loc[3:0] framer ins store ais ins store elastic frm:failure condition mpu_dwfec_rs_t2r_lb (oof/lof/los) insert (for test only) solomon encoder txdata[127:0] spif (from otus) mon & ins dw_es_txdata_en[3:0] dw_es_txsync[3:0]
agere systems inc. 39 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.2 functional description of strong fec (continued) 5.2.1 strong fec mode description all the strong forward error correction (fec) code out-of-band features are supported in digital wrapper mode equipped with overhead byte insertion and monitor. the strong fec code, used to protect the payload/overhead information against transmission errors, is a reed-solomon code specified in itu-t/g.975: rs (255, 239). there is 1 overhead byte, 238 infomation bytes (pay- load and fix stuff), and 16 check bytes per rs (255, 239) code block. the 16 (or 64) rs (255, 239) code blocks are interleaved to form an fec frame. transmission order is column-by-column, i.e., after 16 (or 64) overhead bytes are transmitted, then the first information byte of the second column will be transmitted. the reed-solomon (rs) macro performs out-of-band forward error correction. the encoder generates check bytes of the quad 2488 mbits/s signals or single 9952 mbits/s signal. error correction is performed in the decoder. the rs (255, 239) code shown in figure 27 is a nonbinary code and belongs to the family of systematic linear cyclic block codes. figure 27. 16-way (or 64-way) interleaved rs (255, 239) frame there is 1 framing byte, 238 information bytes (payload and fix stuff), and 16 check bytes per rs (255, 239) code block. in order to enhance the immunity of transmission system to burst errors, 16 (or 64) rs (255, 239) code blocks are interleaved. check data (16 bytes) framing data code block (255 bytes) payload of fec (239 bytes) information (238 bytes) 16 (or 64) code blocks (1 byte)
40 40 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.2 functional description of strong fec (continued) there are five different modes of operation, as shown in table 14. table 14. modes of operation note: digital wrapper (dw) frame mode is equivalent to four multiframe fec frames. in quad 2.5 gbits/s mode, the strong fec macro processes four different 32-bit wide data streams at four different 83 mhz clocks. in 10 gbits/s mode, the strong fec macro processes a single 128-bit wide data stream at a single 83 mhz clock. 16-way or 64-way interleaving is programmable in 10 gbits/s mode, while there is only 16-way inter- leaving in quad 2.5 gbits/s mode. the fec function can be provided as a part of the digital wrapper (dw) frame. the dw frame consists of four fec frames and each fec frame consists of 16-way interleaving rs (255, 239) code blocks, as shown in figure 28. in 16-way interleaving (solid arrow), the overhead columns are spaced by 4064 bytes (254 16 rows/fec frame), while in 64-way interleaving (dashed arrow), all 64 overhead bytes are consecutively transmitted and repeat after 16256 bytes (4 [254 16]). when the strong fec is in dw mode, overhead definition and processing are different from those in fec mode. (see table 7, loss of clock registers, on page 31.) figure 28. digital wrapper?optical channel overhead (16-way/64-way interleaving) table 15 on page 41 shows a summary of the dwfec_mode control registers. fec payload type (dwfec_tx_10g_2g5/ dwfec_rx_10g_2g5) interleaving depth (dwfec_tx_16_64/ dwfec_rx_16_64) oh processing (dwfec_tx_fec_dw/ dwfec_rx_fec_dw) quad 2488 mbits/s 16 fec frame digital wrapper (dw) frame single 9952 mbits/s 16 fec frame digital wrapper (dw) frame 64 digital wrapper (dw) frame fec frame #1 parity data fec frame #2 parity data fec frame #3 parity data fec frame #4 parity data (16 x 2.5 gbits/s/10 gbits/s) (64 x 10 gbits/s) optical overhead bytes (16 per row?total 64) (x16) oh1 oh2 oh3 oh4
agere systems inc. 41 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 5.2.2 strong fec overhead and digital wrapper overhead definition the entire overhead for both fec and dw frames is programmable through the dwac. this allows flexibility in its definition for future changes in the standards. internally, 4 bytes can be monitored with continuous n-times detect (cntd) monitors. these monitors can be combined in four different configurations. they can be grouped as the following: ? four 1-byte monitors. ? two 2-byte monitors. ? one 3-byte and one 1-byte monitor. ? one 4-byte monitor. the multiple bytes do not need to be contiguous. four bytes per stream can be inserted from internal registers. table 16 on page 42 summarizes the overhead sources for each byte in the fec or dw frame. the fec overhead repeats every fec frame. the position and location of the framing bytes are provisionable from a minimum of 2 bytes to a maximum of 16 bytes in steps of 2 bytes. all other bytes that have not been assigned as framing bytes can come from the four internal registers for each 2.5 gbits/s signal or from the dwac. this function can also be provided through software in conjunction with the dwac insert channel. 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.2 functional description of strong fec (continued) table 15. dwfec_mode register summary function register name (first occurrence) register bits qty. 1 1st addr ? (hex) transmit fec payload type indication (2.5 gbits/s or 10 gbits/s) dwfec_mode0 (r/w) dwfec_tx_10g_2g5 1 020f0 transmit interleaving depth control (16-way or 64-way for 10 gbits/s mode only) dwfec_mode0 (r/w) dwfec_tx_16_64 1 020f0 transmit frame indication (fec or dw mode) dwfec_mode1_s0 (r/w) dwfec_tx_fec_dw 4 020f1 receive fec payload type indication (2.5 gbits/s or 10 gbits/s) dwfec_mode0 (r/w) dwfec_rx_10g_2g5 1 020f0 receive interleaving depth control (16-way or 64-way for 10 gbits/s mode only) dwfec_mode0 (r/w) dwfec_rx_16_64 1 020f0 receive frame indication (fec or dw mode) dwfec_mode1_s0 (r/w) dwfec_rx_fec_dw 4 020f1 1. qty. refers to the number of registers that are similar to the one shown in the table. there may be more registers to control different channels, or several registers of similar type used for a particular function. ? 1st addr (hex) refers to the address (in hex) of the first occurrence of this type of register.
42 42 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.2 functional description of strong fec (continued) table 16. fec/digital wrapper overhead source notes: any value not from an internal register or the dwac is set to zero. three bip-8 calculations are provided over the opuk overhead and payload bytes only; other overhead and check bits are excluded from the calculation. the calculated value can be compared against a selected overhead byte. errors are accumulated in three di ffer- ent 27-bit saturating counters. the software and hardware overhead insert priority is defined in table 17. row number frame n frame n + 1 frame n + 2 frame n + 3 fec/dw internal/dwac fec (n)/dw internal/dwac fec (n)/dw internal/dwac fec (n)/dw internal/dwac 1 programmable framing bytes (loca- tion/value?internal), and others from dwac or internal registers (4 max). programmable framing bytes (loca- tion/value?internal), and others from dwac or internal registers (4 max). programmable framing bytes (loca- tion/value?internal), and others from dwac or internal registers (4 max). programmable framing bytes (loca- tion/value?internal), and others from dwac or internal registers (4 max). 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
agere systems inc. 43 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.2 functional description of strong fec (continued) table 17. software/hardware overhead insert priority note: in 10 gbits/s mode, only slice 0 is valid for digital wrapper overhead insert. an otuk overhead format is defined in figure 29. this format (and many others) are permitted (and created) from the internal and dwac capabilities. note: column and row are defined as row and frame, respectively, for register definitions. figure 29. otuk overhead frame structure priority (highest = 1) feature 1 oa1/oa2/mfas byte (software) (section 7 on page 55). 2 ais, oci, or other fixed pattern insert (software, hardware). 3 oh3 (software). 4 oh2 (software). 5 oh1 (software). 6 oh0 (software). 7 bip-8 insert (software). sm (bip0). pm (bip1). tcm (bip2). 8 bei, bdi, iae, or stat insert (software). sm (bei0, bdi0, iae0). pm (bei1, bdi1, stat1). tcm (bei2, bdi2, stat2). 9 dwac insert (dwac, default, passthrough). 10 passthrough (see text on page 61). otuk fec (4 x 256 bytes) otuk payload (4 x 3808 bytes) otuk overhead column row 0 2 1 3 0 15 16 3823 4079 0 1 2 3 01234567 8910 fas mfas sm gcc0 gcc1 aps/pcc res pt 11 12 13 14 15 fec frame # gcc2 res mapping specific res act tcm6 tcm5 tcm4 ftfl tcm3 tcm2 tcm1 pm exp row #
44 44 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.3 strong fec supermacro clocking domain specification in quad 2.5 gbits/s mode, each slice is independent of the others. in loopback mode, clock selection is done in the top-level clock generation block. in 10 gbits/s mode, slice 0 acts as the master slice and all other slices sync to its frame position. in loopback mode, clock selection is done in the top-level clock generation block. 5.4 alarm definition table table 18 summarizes all the service-affecting alarms in the device. table 18. dwfec service-affecting alarm summary interface name definition receive line rxl_loc loss-of-clock (dev_loc_line_rxclk) rxl_los loss-of-signal (frm_rxlos) rxl_oof out-of-frame (frm_rxoof) rxl_lof loss-of-frame (frm_rxlof) rxl_ber_sd ber signal degrade (rs_rxber_sd_det) rxl_ber_sf ber signal fail (rs_rxber_sf_det) rxl_sm_iae sm incoming alignment error (dw_rxiae0_det and dw_txais_tcmstat_iaeinh0) rxl_pm(tcmi)_oci/lck/ais pm (tcmi) stat oci/lck/ais detected (dw_rxoci_det) receive system rxs_es_ovrflw elastic store overflow indicator (es_rx_overflw_a) rxs_es_undrflw elastic store underflow indicator (es_rx_undrflw_a) transmit system txs_es_ovrflw elastic store overflow indicator (es_tx_overflw_a) txs_es_undrflw elastic store underflow indicator (es_tx_undrflw_a) transmit line txl_loc loss-of-clock (dev_loc_line_txclk) txl_los loss-of-signal (frm_txlos) txl_oof out-of-frame (frm_txoof) txl_lof loss-of-frame (frm_txlof)
agere systems inc. 45 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.5 otuk overhead generation table 19. otuk overhead/alarm generation equations bytes subfields generation equation fas ? mpu/dwac mfas ? 0 to 255 repeating sequence sm tti dwac insert bip calculated bei rxl_bip 1 errors 1. rxl_bip = rx_post_cvl_u or rx_post_cvl_l or rx_pre_cvl_u or rx_pre_cvl_l. bdi otuk_sf 2 2. otuk_sf = rxl_loc or rxl_los or rxl_oof or rxl_lof or rxl_ber_sf or rxl_ber_sd or rxl_pm_stat_ais or rxl_ tcmi_stat_ais . iae otuk_sf 2 or txs_cf 3 3. txs_cf (txs_client_failure) = txloc. pm tti dwac insert bip calculated bei rxl_bip 1 errors bdi otuk_sf 2 stat ais?otuk-ais oci?mpu control lck?mpu control psi pt dwac insert msi dwac insert gcc0?gcc2 ? dwac insert tcmi (one at a time internally) ttii dwac insert bipi calculated beii rxl_bip 1 errors bdii otuk_sf 2 stati ais?otuk-ais gen oci?mpu control lck?mpu control ftfl ? mpu/dwac exp ? mpu/dwac aps/pcc ? mpu/dwac
46 46 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.5 otuk overhead generation (continued) table 20. transmit otuk overhead alarm generation and insert control registers bytes subfields generation equation alarm register control register transmit side fas ? mpu/dwac insert ? dw_txoa12_ins, dw_txoa1_val, dw_txoa2_val, dw_txoa12_pairs mfas ? 0 to 255 repeating sequence (available synchronization in loopback mode), mpu/dwac insert ? dw_txmfas_ins, dw_txoa12_mfas sm tti dwac insert ? oh_txl 1 bip calculated ? bip_txl 2 [0] bei rxl_bip errors ? bei_txl 3 [0] bdi otuk_sf_txl 4 dw_txbdi0_det bdi_txl 5 [0] iae otuk_iae_txl 6 dw_txiae0_det dw_txiae0_ins, dw_txiae0_inh, dw_txiae0_lofinh, dw_txiae0_oofinh psi pt dwac insert ? oh_txl 1 msi dwac insert ? oh_txl 1 gcc0?2 ? dwac insert ? oh_txl 1 ftfl ? mpu/dwac ? oh_txl 1 exp ? mpu/dwac ? oh_txl 1 aps/pcc ? mpu/dwac ? oh_txl 1 1. oh_txl = dw_txoh[0?3]_ins, dw_txoh[0?3]_val, dw_txoh[0?3]_frm, dw_txoh[0?3]_row. 2. bip_txl = dw_txbip[0?2]_ins, dw_txbip[0?2]_errins, dw_txbip[0?2]_frm, dw_txbip[0?2]_row. 3. bei_txl = dw_txbei[0?2]_ins, dw_txbei[0?2]_errins, dw_txbii[0?2]_frm, dw_txbii[0?2]_row. 4. otuk_sf_txl = rxl_loc or rxl_los or rxl_oof or rxl_lof or rxl_ber_sf or rxl_ber_sd or rxl_pm_stat_ais or rxl_tcmi_stat_ais. 5. bdi_txl = dw_txbdi[0?2]_ins, dw_txbdi[0?2]_inh, dw_txbdi[0?2]_locinh, dw_txbdi[0?2]_oofinh, dw_txbdi[0?2]_lofinh, dw_txbdi[0?2]_losinh, dw_txbdi[0?2]_sfinh, dw_txbdi[0?2]_sdinh, dw_txbdi[0?2]_aisinh, dw_txbdi[0?2]_ociinh, dw_txbdi[0?2]_fixinh, dw_txbdi[0?2]_timerinh. 6. otuk_iae_txl = rxl_oof or rxl_lof.
agere systems inc. 47 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface pm tti dwac insert ? oh_txl 1 bip calculated ? bip_txl 2 [1] bei rxl_bip errors ? bei_txl 3 [1] bdi otuk_sf_txl 4 dw_txbdi1_det bdi_txl 5 [1] stat ais?otuk-ais generation: otuk_ais_txl = frm = txl_loc or txl_los or txl_oof or txl_lof es or lb = txl_loc or dw_rxais_cond 7 ? dw_txbii1_stat_ins, dw_txais_ins, dw_txoa12_mfas, dw_txloc_aisinh, dw_txoof_aisinh, dw_txlof_aisinh, dw_txlos_aisinh, dw_txrxcond_aisinh, ftfl/tcm/gcc/aps inhibit 8 oci?mpu control: dw_rxoci_cond 9 ? dw_txoci_ins, dw_txrxcond_ociinh, ftfl/tcm/gcc/aps inhibit 8 lck?mpu control: dw_rxfix_cond 10 ? dw_txfix_ins, dw_txlck_fix, dw_txfix_val, dw_txrxcond_fixinh, ftfl/tcm/gcc/aps inhibit 8 tcmi ttii dwac insert ? oh_txl 1 bipi calculated ? bip_txl 2 [2] beii rxl_bip errors ? bei_txl 3 [2] bdii otuk_sf_txl 4 dw_txbdi2_det bdi_txl 5 [2] stati ais?otuk-ais generation ? dw_txbii2_stat_ins, ftfl/tcm/gcc/aps inhibit 8 oci?mpu control ? ftfl/tcm/gcc/aps inhibit 8 lck?mpu control ? ftfl/tcm/gcc/aps inhibit 8 1. oh_txl = dw_txoh[0?3]_ins, dw_txoh[0?3]_val, dw_txoh[0?3]_frm, dw_txoh[0?3]_row. 2. bip_txl = dw_txbip[0?2]_ins, dw_txbip[0?2]_errins, dw_txbip[0?2]_frm, dw_txbip[0?2]_row. 3. bei_txl = dw_txbei[0?2]_ins, dw_txbei[0?2]_errins, dw_txbii[0?2]_frm, dw_txbii[0?2]_row. 4. otuk_sf_txl = rxl_loc or rxl_los or rxl_oof or rxl_lof or rxl_ber_sf or rxl_ber_sd or rxl_pm_stat_ais or rxl_tcmi_stat_ais. 5. bdi_txl = dw_txbdi[0?2]_ins, dw_txbdi[0?2]_inh, dw_txbdi[0?2]_locinh, dw_txbdi[0?2]_oofinh, dw_txbdi[0?2]_lofinh, dw_txbdi[0?2]_losinh, dw_txbdi[0?2]_sfinh, dw_txbdi[0?2]_sdinh, dw_txbdi[0?2]_aisinh, dw_txbdi[0?2]_ociinh, dw_txbdi[0?2]_fixinh, dw_txbdi[0?2]_timerinh. 6. otuk_iae_txl = rxl_oof or rxl_lof. 7. dw_rxais_cond = rxl_loc or rxl_los or rxl_oof or rxl_lof or rxl_ber_sf or rxl_ber_sd or rxl_pm_stat_ais or rxl_tcmi_stat_ais or rxl_ais_byte. 8. dw_txais_ftflinh, dw_txais_tcminh, dw_txais_gccinh, dw_txais_apsinh. 9. dw_rxoci_cond = rxl_pm_stat_oci or rxl_tcmi_stat_oci or rxl_oci_byte. 10. dw_rxfix_cond = rxl_pm_stat_lck or rxl_tcmi_stat_lck or rxl_fix_byte. 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.5 otuk overhead generation (continued) table 20. transmit otuk overhead alarm generation and insert control registers (continued) bytes subfields generation equation alarm register control register
48 48 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.5 otuk overhead generation (continued) table 21. receive otuk overhead alarm generation and insert control registers bytes subfields generation equation alarm/report register control register received side fas ? mpu/dwac drop ? ? mfas ? mpu/dwac drop ? dw_rxoa12_mfas sm tti continuous n-time detect, mpu/dwac drop oh_alarm_rxl 4 oh_rxl 1 bip calculated dw_rxbip01_ecnt bip_rxl 2 [0] bei rxl_bip errors dw_rxbei01_ecnt bei_rxl 3 [0] overwritten before dwac drop (with current calculated bip error per frame value) ? dwac_rxbei0_ovwr bdi continuous n-time detect, mpu/dwac dw_rxbdi0_det dw_rxbdi0_cntd overwritten before dwac drop (with dw_txbdi0_det) ? dwac_rxbdi0_ovwr iae continuous n-time detect, mpu/dwac dw_rxiae0_det dw_rxiae0_cntd overwritten before dwac drop (with dw_txiae0_det) ? dwac_rxiae0_ovwr 1. oh_rxl = dw_rxoh0123_grp, dw_rxoh[0?3]_cntd, dw_rxoh[0?3]_frm, dw_rxoh[0?3]_row. 2. bip_rxl = dw_rxbip[0?2]_disable, dw_rxbip[0?2]_bit_blk, dw_rxbip[0?2]_frm, dw_txbip[0?2]_row. 3. bei_rxl = dw_rxbei[0?2]_disable, dw_rxbei[0?2]_bit_blk, dw_rxbii[0?2]_frm, dw_txbii[0?2]_row. 4. oh_alarm_rxl = dw_rxoh[0?3]_det, dw_rxoh[0?3]_val.
agere systems inc. 49 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface pm tti continuous n-time detect, mpu/dwac drop oh_alarm_rxl 4 oh_rxl 1 bip calculated dw_rxbip11_ecnt bip_rxl 2 [1] bei rxl_bip errors dw_rxbei11_ecnt bei_rxl 3 [1] overwritten before dwac drop (with current calculated bip error per frame value) ? dwac_rxbei1_ovwr bdi continuous n-time detect, mpu/dwac dw_rxbdi1_det dw_rxbdi1_cntd overwritten before dwac drop (with dw_txbdi1_det) ? dwac_rxbdi1_ovwr stat continuous n-time detect, otuk_ais_rxl mpu insert and monitor/dwac drop dw_rx_bii1_stat_new_a, dw_rx_bii1_stat, dw_rxais_det 5 dw_rxbii1_stat_cntd, dw_rxais_setcntd, dw_rxais_clrcntd, dw_rxais_row, dw_rxais_frm, dw_rxais_ins, dw_rxais_detinh, dw_rxloc_aisinh, dw_rxoof_aisinh, dw_rxlof_aisinh, dw_rxlos_aisinh, dw_rxsf_aisinh, dw_rxsd_aisinh, ftfl/tcm/gcc/aps inhibit 6 otuk_oci_rxl mpu insert and monitor/dwac drop dw_rxoci_det 7 dw_rxoci_ins, dw_rxoci_detinh, ftfl/tcm/gcc/aps inhibit 7 otuk_lck_rxl mpu insert and monitor/dwac drop dw_rxfix_det 8 dw_rxfix_val, ftfl/tcm/gcc/aps inhibit 7 psi pt dwac drop ? ? msi dwac drop ? ? gcc0?2 ? dwac drop oh_alarm_rxl 4 oh_rxl 1 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.5 otuk overhead generation (continued) table 21. receive otuk overhead alarm generation and insert control registers (continued) bytes subfields generation equation alarm/report register control register 1. oh_rxl = dw_rxoh0123_grp, dw_rxoh[0?3]_cntd, dw_rxoh[0?3]_frm, dw_rxoh[0?3]_row. 2. bip_rxl = dw_rxbip[0?2]_disable, dw_rxbip[0?2]_bit_blk, dw_rxbip[0?2]_frm, dw_txbip[0?2]_row. 3. bei_rxl = dw_rxbei[0?2]_disable, dw_rxbei[0?2]_bit_blk, dw_rxbii[0?2]_frm, dw_txbii[0?2]_row. 4. oh_alarm_rxl = dw_rxoh[0?3]_det, dw_rxoh[0?3]_val. 5. dw_rxais_det = rxl_pm_stat_ais or rxl_tcmi_stat_ais or rxl_ais_byte. 6. dw_rxais_ftflinh, dw_rxais_tcminh, dw_rxais_gccinh, dw_rxais_apsinh. 7. dw_rxoci_det = rxl_pm_stat_oci or rxl_tcmi_stat_oci or rxl_oci_byte. 8. dw_rxfix_det = rxl_pm_stat_lck or rxl_tcmi_stat_lck or rxl_fix_byte.
50 50 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface tcmi tti continuous n-time detect, mpu/dwac drop oh_alarm_rxl 4 oh_rxl 1 bip calculated dw_rxbip21_ecnt bip_rxl 2 [2] bei rxl_bip errors dw_rxbei21_ecnt bei_rxl 3 [2] overwritten before dwac drop (with current calculated bip error per frame value) ? dwac_rxbei2_ovwr bdi continuous n-time detect, mpu/dwac dw_rxbdi2_det dw_rxbdi2_cntd overwritten before dwac drop (with dw_txbdi2_det) ? dwac_rxbdi2_ovwr stat continuous n-time detect, otuk_ais_rxl mpu insert and monitor/dwac drop dw_rx_bii2_stat_new_a, dw_rx_bii2_stat, dw_rxais_det 6 dw_rxbii2_stat_cntd, ftfl/tcm/gcc/aps inhibit 7 otuk_oci_rxl mpu insert and monitor/dwac drop dw_rxoci_det 7 ftfl/tcm/gcc/aps inhibit 7 otuk_lck_rxl mpu insert and monitor/dwac drop dw_rxfix_det 8 ftfl/tcm/gcc/aps inhibit 7 ftfl ? mpu/dwac drop ? oh exp ? mpu/dwac drop ? oh aps/pcc ? mpu/dwac drop oh_alarm_rxl 4 oh_rxl 1 1. oh_rxl = dw_rxoh0123_grp, dw_rxoh[0?3]_cntd, dw_rxoh[0?3]_frm, dw_rxoh[0?3]_row. 2. bip_rxl = dw_rxbip[0?2]_disable, dw_rxbip[0?2]_bit_blk, dw_rxbip[0?2]_frm, dw_txbip[0?2]_row. 3. bei_rxl = dw_rxbei[0?2]_disable, dw_rxbei[0?2]_bit_blk, dw_rxbii[0?2]_frm, dw_txbii[0?2]_row. 4. oh_alarm_rxl = dw_rxoh[0?3]_det, dw_rxoh[0?3]_val. 5. dw_rxais_det = rxl_pm_stat_ais or rxl_tcmi_stat_ais or rxl_ais_byte. 6. dw_rxais_ftflinh, dw_rxais_tcminh, dw_rxais_gccinh, dw_rxais_apsinh. 7. dw_rxoci_det = rxl_pm_stat_oci or rxl_tcmi_stat_oci or rxl_oci_byte. 8. dw_rxfix_det = rxl_pm_stat_lck or rxl_tcmi_stat_lck or rxl_fix_byte. 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.5 otuk overhead generation (continued) table 21. receive otuk overhead alarm generation and insert control registers (continued) bytes subfields generation equation alarm/report register control register
agere systems inc. 51 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.6 strong fec alarm actions table 22. alarm actions interface name action on detection monitoring (all modes) maintence signal generation (terminal/regenerator/ bidirectional modes) receive line (otuk input data interface) rxl_loc disable all monitoring oduk-ais if enabled rxl_los disable all monitoring oduk-ais if enabled rxl_oof disable all monitoring oduk-ais if enabled rxl_lof disable all monitoring oduk-ais if enabled rxl_ber_sf allow monitoring oduk-ais if enabled rxl_ber_sd allow monitoring oduk-ais if enabled rxl_iae allow monitoring no action rxl_tcmi_stat_ais disable all monitoring regenerate oduk-x maintenance signal if enabled rxl_tcmi_stat_oci rxl_tcmi_stat_lck rxl_pm_stat_ais disable all monitoring regenerate oduk-x maintenance signal if enabled rxl_pm_stat_oci rxl_pm_stat_lck receive system (client output data interface) rxs_es_ovrflw na no action rxs_es_undrflw na no action transmit system (client input data interface) txs_es_ovrflw na no action txs_es_undrflw na no action transmit line (otuk output data interface) txl_loc na oduk-ais if enabled txl_oof (bidirectional mode only) na oduk-ais if enabled txl_lof (bidirectional mode only) na oduk-ais if enabled txl_los (bidirectional mode only) na oduk-ais if enabled
52 52 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.7 overview, general functional description, and block diagram of strong fec supermacro submacros 5.7.1 elastic store (es) macro the es macro performs rate conversion between two different clocks. one clock (83 mhz) is faster than the other (78 mhz), but the effective clock rates are the same because the faster clock has overhead bytes; therefore, there is no stuffing mechanism. the transmit es buffers system rate data and outputs gapped line rate data to create space for fec/dw overhead and fec check bytes. data arrives at the transmit es grouped as 32 bits in each slice. each group of 32 bits is written into the associated es location (128 locations 32 bits). in 2.5 gbits/s mode, data is read from the es by 238 clock cycles per 255 clock cycles. in 10 gbits/s mode, data can either be read by 237 or 238 clock cycles per 255 clock cycles depending on the phase detector divide ratio settings. the receive es buffers gapped data at the line rate and outputs data at the system rate to absorb clock gapping of the fec/dw overhead and fec check bytes. data arrives to the receive es grouped as 32 bits in each slice. each group of 32 bits is written into the associated es location (128 locations 32 bits) by 238 clock cycles (for 2.5 gbits/s mode) or 237/238 clock cycles (depending on the phase detector divide ratio settings for 10 gbits/s fec/dw frame) per 255 clock cycles per the system rate clock. an optional fixed stuff row can be placed in row 120 of 255 in 10 gbits/s mode. 5.7.2 dw macro this block controls the creation of the fec/dw frame by controlling the read/write pointers to the elastic store. this control allows gap to be inserted into the outgoing frame for overhead, stuff column, and check byte insertion. the overhead is provisionable through internal registers or through the dwac channel. 5.7.3 reed-solomon (rs) macro the rs macro performs out-of-band forward error correction using the rs (255, 239) code. the rs encoder accepts 239 bytes of payload and overhead data followed by 16 bytes of all-zero check bytes, and generates 16 bytes of check data. the rs decoder detects and corrects transmission errors, then calculates and reports the incoming ber based on the exact number of corrected bits. 5.7.4 scrambler/descrambler macro the scrambler/descrambler optionally scrambles/descrambles data. the scrambling sequence can be selected between two different polynomials: x 7 +x+1 or x 16 +x 12 +x 3 + x + 1. once a scrambling/descrambling pattern is requested, the entire frame (with the exception of the framing bytes) is scrambled/descrambled by the selected polynomial, starting at each frame on the first bit which follows the last framing byte.
agere systems inc. 53 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 5 strong fec (reed-solomon and digital wrapper) supermacro (continued) 5.7 overview, general functional description, and block diagram of strong fec supermacro submacros (continued) 5.7.5 error insert macro the error insert macro inserts various types of errors for rs codec testing. errors can be inserted in 32-bit format in quad 2.5 gbits/s mode, or in 128-bit format in 10 gbits/s mode. 5.7.6 framer macro data arrives to the fec/dw framer grouped as 4 slices of 4 bytes (32 bits) in quad 2.5 gbits/s mode, and 16 bytes (128 bits) in single 10 gbits/s mode. the fec/dw framer performs the following: framing detects los, oof, lof descrambles the data inserts ais in 10 gbits/s mode, a single fec/dw framer works on a 128-bit wide data bus. in quad 2.5 gbits/s mode, a sepa- rate fec/dw framer works on each 32-bit wide data bus; therefore, there are four separate fec/dw framers for four different slices. 5.7.7 interleaver/deinterleaver macro the rs encoder/decoder performs byte interleaving/deinterleaving of code blocks in order to enhance the immu- nity of transmission system to burst errors (in byte manner).
54 54 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 6 strong fec supermacro elastic store (transmit direction) 6.1 elastic store (tx) functional description the transmit es buffers system rate data and outputs gapped line rate data to allocate space for fec/dw over- head and fec check bytes. it is assumed that the effective clocks of both write and read are the same; therefore, there is no stuffing mechanism. data arrives to the transmit es grouped as 32 bits in each slice. each group of 32 bits is always written into the associated es location (128 locations 32 bits), even if the es will over- flow/underflow. data is read from the es by the line rate clock for 238 or 237 out of 255 clock cycles for each fec frame. the relationship between read and write address is controlled in order to simultaneously minimize signal delay and to guarantee data integrity. at the initial state, or after overflow/underflow, the read address is automatically reset to the predefined position (32 locations ahead of the write address), when the first sync pulse is received. in 10 gbits/s mode, all four elastic stores work in synchronization. in some applications, the transmit es is disabled and data is bypassed. in this case, the overflow/underflow alarm is not declared. the es can be forced to restart by software control. table 23. elastic store (tx) register summary function register name (first occurrence) register bits qty. 1st addr (hex) tx es overflowing interrupt alarm es_alarm_s0 (w1c) es_tx_overflw_a 4 0201c tx es underflowing interrupt alarm es_alarm_s0 (w1c) es_tx_undrflw_a 4 0201c tx es overflowing interrupt alarm mask es_mask_s0 (r/w) es_tx_overflw_m 4 02058 tx es underflowing interrupt alarm mask es_mask_s0 (r/w) es_tx_undrflw_m 4 02058 tx es forced restart es_ctl_s0 (r/w) es_tx_restart 4 02130
agere systems inc. 55 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 7 strong fec supermacro fec/dw framer (los, oof, lof) 7.1 functional description of fec/dw framer the fec/dw framer consists of three subblocks: a loss-of-signal (los) detector, fec/dw framer (oa1 and oa2), and a frame state machine (for detection of oof and lof). the los detector monitors the data for loss of signal (fixed all-zeros pattern over a programmable time interval). the fec/dw framer block allows the framing on a dw or fec frame based on a programmable value/number of oa1 and oa2 bytes. the lof detector monitors the oof state for a continuous in-frame or out-of-frame state. 7.1.1 loss-of-signal (los) detector the data is monitored by the los detector macro for loss of signal (los). in 10 gbits/s mode, there is a single los detector. in quad 2.5 gbits/s mode, there is a separate los detector on each quad input. on powerup, an los defect is declared if all-zeros data is received continuously for a programmable time threshold. this time threshold is provisionable through the loss-of-signal (los) threshold register (frm_tx_ctl_losdet, 0x22b4) for each slice. the default value is 0 (disabled). assuming that the client signal is operating at sonet or sdh clock rates, the threshold can be set to any value from 0 s (i.e., los detection disabled) to 98.32 s, with a resolution of 96.02 ns. in the event that other line clock rates are used, the resolution of the threshold is determined by multiplying the period of the line clock by 64. an los defect is subsequently cleared when two successive valid framing patterns are received with no period of all zeros exceeding the time threshold. detection of an los defect is indicated by a latched alarm status bit and a persistency bit. four los detectors are implemented, corresponding to each slice. in quad 2.5 gbits/s mode, all the los detectors function independently on 32 bits of data. in 10 gbits/s mode, the slice 0 los detector functions on 128 bits of data and the other los detectors are disabled. if the los detect threshold is set to zero, los detection is disabled and los and los_pm outputs are deasserted regardless of the los condition. the slice 0 los detector pin descrip- tion is given in table 24. if an optical transponder is connected to the receive line interface, the most appropriate method to declare los is by monitoring the power level monitor of the received signal from the transponder. in some transponders, the amplifier gain is high enough to cause the lvds receive data lines to move above zero, even when there is no opti- cal output. if this should occur, the tfec0410g may not indicate an los defect. this is not a deficiency of the device, but a characteristic of the los detection methods. if an optical transponder is used, the los detector of the tfec0410g monitors the connection from the transponder to the receive line interface. the los detector in the tfec0410g is appropriate for electrical monitoring of los. table 24. los detector register summary function register name (first occurrence) register bits qty. 1st addr (hex) los detect time threshold frm_tx_ctl_losdet_s0 (r/w) frm_txlos_det 4 022b4 los interrupt alarm frm_alarm_s0 (w1c) frm_txlos_a 4 0202c los alarm mask frm_mask_s0 (r/w) frm_txlos_m 4 02068 los persistency frm_persist_s0 (ro) frm_txlos_p 4 0209c los state frm_state_s0 (ro) frm_txlos 4 020cc
56 56 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 7 strong fec supermacro fec/dw framer (los, oof, lof) (continued) 7.1 functional description of fec/dw framer (continued) 7.1.2 framer (a1 and a2) in 10 gbits/s mode, framing is performed on a single channel. in quad 2.5 gbits/s mode, framing is performed on four independent channels. the frame alignment is found by searching for the oa1 and oa2 bytes contained in the fec/dw (och) signal. the framing pattern searched for, or checked, may be a subset of the oa1 and oa2 bytes contained in the fec/dw (och) signal. the framed signal is continuously checked with the presumed frame start position for the alignment. if in the in-frame state (oof = 0), the maximum out-of-frame (oof) detection time will be equal to a programmable period of fec/dw (och) frames (superframes). if in the oof state, the maximum frame alignment time will be equal to a programmable number of the fec/dw (och) frame (superframe) periods of an error-free signal with no emulated framing patterns. the number of oa1 and oa2 bytes are programmable independently while in the in-frame state and out-of-frame state. the framer outputs frame-aligned data and an 8 khz sync and reference (free-running) signals. the oa1 pattern cannot be aliased within the oa1 and oa2 pattern boundary. also, under no circumstances can the two patterns, oa1 and oa2, be the same. four framers are implemented, corresponding to each slice. in quad 2.5 gbits/s mode, all framers function inde- pendently on 32 bits of data. in 10 gbits/s mode, the slice 0 framer functions on 128 bits of data and the other fram- ers are disabled. if the frm_dis signal is asserted, framing is disabled. in loopback mode, the framer outputs are disabled and the output sync follows the incoming sync. 7.1.2.1 frame state machine (fsm) the fsm is responsible for bit/byte rotation and for determining the out-of-frame state (oof) and loss-of-frame (lof) alarms for each channel. the fsm comes out of reset in the oof state with the oof and lof alarms active. the framining parameters are summarized below: 1. oa1, oa2 programmable value per slice (mpu_dw_frm_oa1_val[3?0][7:0], mpu_dw_frm_oa2_val[3?0][7:0]). 2. number of framing pattern pairs (oa1/oa2) in the fec/dw (och) frame (mpu_dw_frm_oa12_pairs[3?0][2:0]; see table 25). 3. number of framing pattern pairs (oa1/oa2) used to transition between out-of-frame to in-frame state (oof, 1 ? 0), mpu_dw_frm_oa12_pairclr[3?0][2:0]. 4. number of framing pattern pairs (oa1/oa2) used to transition between in-frame to out-of-frame state (oof, 0 ? 1), mpu_dw_frm_oa12_pairset[3?0][2:0]. 5. number of valid consecutive framing pairs (oa1/oa2) required to transition from out-of-frame to the in-frame state (mpu_dw_frm_oof_clr[3?0][4:0]). when a portion of the frame alignment word is used, the pattern is always equally centered around the oa1/oa2 border. 6. number of valid consecutive framing patterns (oa1/oa2) required to transition from in-frame to the out-of-frame state (mpu_dw_frm_oof_set[3?0][4:0]). when a portion of the frame alignment word is used, the pattern is always equally centered around the oa1/oa2 border.
agere systems inc. 57 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 7 strong fec supermacro fec/dw framer (los, oof, lof) (continued) 7.1 functional description of fec/dw framer (continued) table 25. frame alignment (oa1, oa2) pattern positions the following example defines a frame pattern that contains three oa1 and three oa2 frame alignment words (a in figure 30, framing algorithm with example, on page 58) with values 0xf6 and 0x28 (b, c), respectively. all six framing values are required to be error free for two consecutive frames for transition from the out-of-frame state to the in-frame state (d). after six consecutive mismatches (e), the out-of-frame state is entered. only two of the frame alignment words (containing the oa1/oa2 border) are tested for mismatches. note that the framer will not generate sync pulses during the oof state. note: the minimum oof set value is 02. if oof_set is programmed to 00 or 01, oof will be declared after two consecutive mismatches. value (pairs) 12345678910111213141516 0x0 (1) 1 1. 0x0 (1) is the default value. oa1oa2?????????????? 0x1 (2) oa1oa1oa2oa2???????????? 0x2 (3) 2 2. 0x2 (3) is defined by itu-t/g.709. oa1oa1oa1oa2oa2oa2?????????? 0x3 (4) oa1oa1oa1oa1oa2oa2oa2oa2???????? 0x4 (5) oa1oa1oa1oa1oa1oa2oa2oa2oa2oa2?????? 0x5 (6) oa1 oa1 oa1 oa1 oa1 oa1 oa2 oa2 oa2 oa2 oa2 oa2 ? ? ? ? 0x6 (7) oa1 oa1 oa1 oa1 oa1 oa1 oa1 oa2 oa2 oa2 oa2 oa2 oa2 oa2 ? ? 0x7 (8) oa1 oa1 oa1 oa1 oa1 oa1 oa1 oa1 oa2 oa2 oa2 oa2 oa2 oa2 oa2 oa2
58 58 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 7 strong fec supermacro fec/dw framer (los, oof, lof) (continued) 7.1 functional description of fec/dw framer (continued) figure 30. framing algorithm with example framing pattern reset oof frame confirmed framing pattern found framing pattern not comfirmed programmable consecutive framing errors confirm in frame (b) mpu_dw_frm_oa1_val[7:0] = 0xf6 (c) mpu_dw_frm_oa2_val[7:0] = 0x28 (a) mpu_dw_frm_oa12_pairs[2:0] = 0x2 mpu_dw_frm_oa12_pairclr[2:0] = 0x2 mpu_dw_frm_oa12_pairset[2:0] = 0x0 (d) mpu_dw_frm_oof_clr[4:0] = 0x1 (e) mpu_dw_frm_oof_set[4:0] = 0x6 mpu_dw_frm_disable = 0
agere systems inc. 59 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 7 strong fec supermacro fec/dw framer (los, oof, lof) (continued) 7.1 functional description of fec/dw framer (continued) table 26. framer control register summary function register name (first occurrence) register bits qty. 1st addr (hex) framer disable frm_tx_ctl_oof_3_s0 (r/w) frm_tx_disable 4 022c0 oa1 frame byte value frm_tx_ctl_oa12_s0 (r/w) frm_txoa1_val 4 022b8 oa2 frame byte value frm_tx_ctl_oa12_s0 (r/w) frm_txoa2_val 4 022b8 number of repeat oa1 bytes (same as oa2) ex: 0 = one oa1, one oa2s 7 = eight oa1s, eight oa2s see table 25 on page 57 frm_tx_ctl_oa12_pat_3_s0 (r/w) frm_txoa12_pairs 4 022bc number of framing pattern pairs (oa1/oa2) used to transition between out-of-frame to in-frame state (oof, 1 0) frm_tx_ctl_oa12_pat_3_s0 (r/w) frm_txoa12_pairclr 4 022bc number of framing pattern pairs (oa1/oa2) used to transition between in-frame to out-of-frame state (oof, 0 1) frm_tx_ctl_oa12_pat_3_s0 (r/w) frm_txoa12_pairset 4 022bc out-of-frame set frm_tx_ctl_oof_3_s0 (r/w) frm_txoof_set 4 022c0 out-of-frame clear frm_tx_ctl_oof_3_s0 (r/w) frm_txoof_clr 4 022c0 out-of-frame interrupt alarm frm_alarm_s0 (w1c) frm_txoof_a 4 0202c out-of-frame interrupt alarm mask frm_mask_s0 (r/w) frm_txoof_m 4 02068 out-of-frame persistency frm_persist_s0 (ro) frm_txoof_p 4 0209c out-of-frame state frm_state_s0 (ro) frm_txoof 4 020cc
60 60 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 7 strong fec supermacro fec/dw framer (los, oof, lof) (continued) 7.1 functional description of fec/dw framer (continued) 7.1.3 loss-of-frame (lof) detector the lof alarm is asserted if oof persists for a programmable number of frames. the lof alarm is terminated a programmable number of frames after the oof alarm is terminated. an interrupt alarm, persistency, and state are provided per slice. table 27. loss-of-frame control register summary 7.1.4 provisioning and alarm operation in 10 gbits/s mode only slice 0 alarms and control parameters are valid in 10 gbits/s mode. all other slice information is ignored and all alarms from slice 1, slice 2, and slice 3 are disabled. function register name (first occurrence) register bits qty. 1st addr (hex) loss-of-frame set frm_rx_ctl_lof_2_s0 (r/w) frm_txlof_set 4 022c4 loss-of-frame clear frm_rx_ctl_lof_2_s0 (r/w) frm_txlof_clr 4 022c4 loss-of-frame interrupt alarm frm_alarm_s0 (w1c) frm_txlof_a 4 0202c loss-of-frame interrupt alarm mask frm_mask_s0 (r/w) frm_txlof_m 4 02068 loss-of-frame persistency frm_persist_s0 (ro) frm_txlof_p 4 0209c loss-of-frame state frm_state_s0 (ro) frm_txlof 4 020cc
agere systems inc. 61 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert 8.1 functional description of digital wrapper insert the digital wrapper insert is used for overhead processing before the reed-solomon (rs) encoder (check byte insert). all overhead and data can be retimed and passed through by enabling the control bit, dw_tx_passthru. passthrough mode is only available when the data is coming from the transmit framer or is looped back from the receive direction. see table 17, software/hardware overhead insert priority, on page 43 and figure 26, strong fec supermacro, on page 38 for more information. table 28. digital wrapper input mux control register summary all fec/dw frame overhead insert functions supported by the dw in the transmit direction are summarized as fol- lows: frame bytes insert. multiframe byte (free-running) insert. internal fec overhead bytes insert. bip-8 calculation. bei/bdi insert and monitor. iae/stat insert and monitor. ais, oci, or other pattern insert. dwac insert. prbs payload insert. check bits insert. fixed stuff column enable/disable. the 128-bit input data can be selected from either es_dw_txdata[127:0] or frm_dw_txdata[127:0] via the microprocessor. in loopback mode, the 128-bit input data can be selected from the output of the receive direction (dw_es_rxdata) to pass through to the digital wrapper insert, which is controlled by the top-level input pin (mpu_dw_r2t_lb). the digital wrapper insert should synchronize its frame by monitoring dw_es_rxsync. function register name (first occurrence) register bits qty. 1st addr (hex) transmit input mux. the dw insert block will take the following data to process: 0 = es_dw_txdata (from tx es). 1 = frm_dw_txdata (from tx framer). dwfec_mux_s0 (r/w) dw_tx_es_frm 4 020f5 transmit overhead passthrough mode: 0 = disable. 1 = enable. overhead passthrough should only be enabled when data is coming from the tx framer or from the rx direction loopback (rdw2tdw_lb). dw_tx_ctl_top_2_s0 (r/w) dw_tx_passthru 4 02178
62 62 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) 8.1.1 framing bytes insert the dw macro allows programmable framing bytes (oa1, oa2) in both fec frame and dw (multiframe) mode. for g.709 compliance, the framing bytes should be set as follows: set the oa1 byte to 0xf6. set the oa2 byte to 0x28. set the insertion count to 0x2. set the number of mfas bytes to 0x1. in the transmit direction, a free-running counter generates the mfas bytes. in loopback or bidirectional mode, the mfas counter is synchronized to the incoming mfas. the dwac sync output is asserted for two dwac clock cycles wide to indicate that the current overhead is for mfas 0x0. (see figure 40 on page 79.) all framing bytes can be inserted by either the dwac insert channel or by one or all of the overhead (ohx) insert bytes. when neither oa1 nor oa2 is inserted, either the dwac insert byte, overhead (ohx) insert bytes, or default will be inserted. dw_txdefault will set all overhead bytes to a default value of all 1s or 0s if no specific overhead insertion is enabled. table 29. framing byte (oa1 and oa2) insert control register summary function register name (first occurrence) register bits qty. 1st addr (hex) oa1 oa2 frame byte insert enable dw_tx_ctl_top_2_s0 (r/w) dw_txoa12_ins 4 02178 oa1 frame byte value dw_tx_ctl_oa12_s0 (r/w) dw_txoa1_val 4 0217c oa2 frame byte value dw_tx_ctl_oa12_s0 (r/w) dw_txoa2_val 4 0217c number of repeat oa1 and oa2 byte pairs (see table 25 on page 57) dw_tx_ctl_oa12_pat_s0 (r/w) dw_txoa12_pairs 4 02180 insert free-running mfas counter dw_tx_ctl_top_v2_s0 (r/w) dw_txmfas_ins 4 02514 default value for overhead bytes (all 0s or all 1s) dw_tx_ctl_top_2_s0 (r/w) dw_txdefault 4 02178 sync mfas counter to incoming mfas value enable dw_tx_ctl_top_v2_s0 (r/w) dw_txmfas_sync 4 02514
agere systems inc. 63 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) 8.1.2 internal fec overhead byte insert (oh0 to oh3) there are four internal programmable bytes (oh0, oh1, oh2, oh3) that can be inserted or overwritten in digital wrapper overhead locations for each slice. each overhead (ohx) can be inserted by programming its 8-bit wide value. the location of the overhead byte can be specified by using frame location and row location. note: column and row are defined as row and frame, respectively, for register definitions. figure 31. internal dwfec overhead byte insert programmable location example example: insert oh0 value 020 into gcc1, byte 0; oh location is frm 3, row 1 dw_oh0_ins[0] = 1 dw_txoh0_val[0][7:0] = 020 dw_txoh0_frm[0][1:0] = 01 (01) dw_txoh0_row[0]03:0] = 0100 (04) 0 1 2 3 01234567 89101112131415 fec frame # row #
64 64 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface note: refer to table 12 on page 35 for the priority of overhead byte insert. in fec frame, only row location control registers are used. 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) table 30. transmit dw oh0 to oh3 bytes register summary function register name (first occurrence) register bits qty. 1st addr (hex) overhead byte insertion enable dw_tx_ctl_top_2_s0 (r/w) dw_txoh0_ins 4 02178 overhead byte insertion value dw_tx_ctl_oh0_2_s0 (r/w) dw_txoh0_val 4 02184 overhead byte insertion frame location (dw mode only) dw_tx_ctl_oh0_2_s0 (r/w) dw_txoh0_frm 4 02184 overhead byte insertion row location dw_tx_ctl_oh0_2_s0 (r/w) dw_txoh0_row 4 02184 overhead byte insertion enable dw_tx_ctl_top_2_s0 (r/w) dw_txoh1_ins 4 02178 overhead byte insertion value dw_tx_ctl_oh1_2_s0 (r/w) dw_txoh1_val 4 02188 overhead byte insertion frame location (dw mode only) dw_tx_ctl_oh1_2_s0 (r/w) dw_txoh1_frm 4 02188 overhead byte insertion row location dw_tx_ctl_oh1_2_s0 (r/w) dw_txoh1_row 4 02188 overhead byte insertion enable dw_tx_ctl_top_2_s0 (r/w) dw_txoh2_ins 4 02178 overhead byte insertion value dw_tx_ctl_oh2_2_s0 (r/w) dw_txoh2_val 4 0218c overhead byte insertion frame location (dw mode only) dw_tx_ctl_oh2_2_s0 (r/w) dw_txoh2_frm 4 0218c overhead byte insertion row location dw_tx_ctl_oh2_2_s0 (r/w) dw_txoh2_row 4 0218c overhead byte insertion enable dw_tx_ctl_top_2_s0 (r/w) dw_txoh3_ins 4 02178 overhead byte insertion value dw_tx_ctl_oh3_2_s0 (r/w) dw_txoh3_val 4 02190 overhead byte insertion frame location (dw mode only) dw_tx_ctl_oh3_2_s0 (r/w) dw_txoh3_frm 4 02190 overhead byte insertion row location dw_tx_ctl_oh3_2_s0 (r/w) dw_txoh3_row 4 02190
agere systems inc. 65 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) 8.1.3 bip-8 calculation three bip-8 calculations are provided every frame (opu overhead (row 14?15), payload, and fix stuff; other bytes are excluded from calculation). the bit interleaved parity code (bip-8) byte is even parity, which is placed in the bip byte of the second frame following the frame as shown in figure 32. note: refer to table 17 on page 43 for the priority of overhead byte insert. in fec frame, only row location control registers are used. figure 32. g.709 bip-8 computation and transport for one connection monitoring level the bip-8 byte can be inserted via microprocessor control. the bip-8 byte can be inserted in both fec and dw frames by specifying the location (time slot) of any frame. this is identical to the example in figure 32. bip-8 insert is suggested to be inserted at the corresponding locations of the sm/tcm and pm bytes. bip8 bip8 bip8 0 1 2 3 0 1 2 3 0 1 2 3 payload 13 1415 16 frame i frame i +2 0 4079 bytes 3823 frame i + 1
66 66 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) 8.1.4 general definition of bei, bdi, and iae insert and monitor three bii bytes can be inserted in every frame. a bii byte includes bei (the number of bip errors per frame in the receive direction) and bdi interrupt alarm state. the bei value is between 0 to 8 in each frame. when bei insert is disabled, bei location is set to zero. when bei error insert is enabled, bei location is set to a nonzero fixed value. figure 33. bii byte description each bdi-failure (dw_txbdi0_ins, dw_txbdi1_ins, and dw_txbdi2_ins) contributes to a state bit. transmit bdi-failure is inserted into the data signal using the following equation: dw_txbdi_det = (line_rx83loc and not (dw_txbdi_locinh)) or?input loss of clock (frm_rxlos and not (dw_txbdi_losinh)) or?loss-of-signal (frm_rxoof and not (dw_txbdi_oofinh)) or?out-of-frame (frm_rxlof and not (dw_txbdi_lofinh)) or?loss-of-frame (rs_rxber_sf_det and not (dw_txbdi_sfinh)) or?ber signal fail (rs_rxber_sd_det and not (dw_txbdi_sdinh)) or?ber signal degrade (dw_rxais_cond and not (dw_txbdi_aisinh)) or?pm-ais or tcm-ais (dw_rxoci_cond and not (dw_txbdi_ociinh)) or?pm-oci or tcm-oci (dw_rxfix_cond and not (dw_txbdi_fixinh)) or?pm-fix/lck or tcm-lck (timer20frames and not (dw_txbdi_timerinh)) or?20 frame timer (dw_txbdi_ins)?software insert only receive alarms can contribute to transmit bdi failure generation. transmit framer alarms and loss-of-transmit clock do not contribute to transmit bdi. note: refer to table 17, software/hardware overhead insert priority, on page 43 for the priority of overhead byte insert. in fec frame mode, only row location control registers are used. for bei error insert, set bei to a value of 0x3 regardless of the number of receive direction bip errors per frame. bei and bdi can be passthrough or inserted indepedently by using the dwac insert. if bdi is inserted for a bdi overwritten byte in dwac drop in the receive direction, and it is not desired to generate bdi in the transmit direction, the bii byte location can be programmed to an invalid location; bei insert is also disabled. sonet/sdh equipment has the ability to generate an rdi-p alarm for a minimum number of frames. the 20-frame timer allows for a similar function in bdi generation. this may be inhibited through software if not desired. bdi bei (bip error per frame) bii0 byte bdi bii1/bii2 byte stat iae
agere systems inc. 67 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) a single-bit iae is also generated in the transmit direction. it is generated under oof/lof conditions in the receive direction. only receive alarms can contribute to transmit iae failure generation. transmit framer alarms do not con- tribute to transmit iae. dw_txiae_det = (frm_rxoof and not (dw_txiae_oofinh)) or?out-of-frame (frm_rxlof and not (dw_txiae_lofinh)) or?loss-of-frame (dw_txiae_ins)?software insert bdi/bei/iae are controlled individually by the corresponding sm/pm and tcm control signals described in section 8.1.5 on page 68 through section 8.1.9 on page 76. table 31. bdi/iae overhead insert priority figure 34 shows the bdi and iae alarm detection and insertion structure. figure 34. bdi and iae alarm structure (per slice) priority (highest = 1) feature 1 software bdi/iae insert (ex., dw_txbdi0_ins is set high) 2 hardware bdi/iae detect = dw_txbdi0_det (ex., dw_txbdi0_inh or dw_txiae0_inh is set low) 3dwac insert 4 passthrough frm_rxoof dw_txiae_oofinh frm_rxlof dw_txiae_lofinh dw_txiae_ins frm_rxlos dw_txbdi_losinh rs_sf dw_txbdi_sfinh rs_sd dw_txbdi_sdinh dw_txiae_det dw_txiae_ins (iae overhead bit insert) dw_txiae_inh frm_rxlof dw_txbdi_lofinh frm_rxoof dw_txbdi_oofinh dw_rxais_cond dw_txbdi_aisinh line_rx83loc dw_txbdi_locinh dw_rxoci_cond dw_txbdi_ociinh dw_rxfix_cond dw_txbdi_fixinh dw_txbdi_det dw_txbdi_ins (bdi overhead bit insert) dw_txbdi_inh
68 68 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) table 32. oduk tcm-stat overhead interpretation if (ais_cond_insert = 1), then: 8.1.5 otu section monitoring (sm) one field of section monitoring overhead (sm) is defined in fec frame 0, rows 7 to 9, to support section monitor- ing. the sm field contains the following subfields (figure 35). these bytes will use the bip0 set of register bits (dw_txbip0_ins, etc.) in the insert control registers. bit interleaved parity (bip-8). backward defect indication (bdi). backward error indication (bei). incoming alignment error overhead (iae). reserved for future international standardization (res). figure 35. g.709 oduk section monitor overhead stat[2:0] status 000 no source tc 001 in use without iae condition (normal or otuk-ais 1 ) 1. during otuk-ais, dw_txais_tcmstat_iaeinh is set high. 010 in use with iae condition (dw_txiae0_det and not dw_txais_tcmstat_iaeinh) 011 reserved for future international standardization 100 reserved for future international standardization 101 maintenance signal: oduk-lck 110 maintenance signal: oduk-oci 111 maintenance signal: oduk-ais 0 15 tti bip-8 12 3 76543210 bei bdi iae res sm-3 16 31 32 63 sm sapi dapi operator specific
agere systems inc. 69 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) 8.1.5.1 sm bit interleaved parity (bip-8) one bip-8 calculation is provided in the section monitoring (sm) field (over payload and opu overhead, check bits are excluded from calculation of the frames); see figure 32. the section (even parity) bit interleaved (bip-8) byte?s value is calculated over the entire opu signal in the nth frame and then inserted in the bip byte of the n + 2nd frame as shown in figure 32 on page 65. the computed bip-8 byte can then be error inserted (bits are inverted) via microprocessor control. table 33. transmit sm bip byte insertion register summary 8.1.5.2 sm backward error indication (bei) the bei (bip errors per frame in the receive direction) can be inserted in every frame to indicate to the far end the received bip errors. the valid bei value is between 0 and 8 in each frame; invalid values that are greater than 0x8 are set as zero. when bei insert is disabled, bei value is set to zero. when bei error insert is enabled, bei value is set to a 0x3 regardless of the number of received bip errors per frame. table 34. transmit sm bei insertion register summary function register name (first occurrence) register bits qty. 1st addr (hex) bip byte insertion enable dw_tx_ctl_bip_s0 (r/w) dw_txbip0_ins 4 02198 bip byte error insertion enable dw_tx_ctl_bip_s0 (r/w) dw_txbip0_errins 4 02198 bip byte insertion frame location dw_tx_ctl_bip_s0 (r/w) dw_txbip0_frm 4 02198 bip byte insertion row location dw_tx_ctl_bip_s0 (r/w) dw_txbip0_row 4 02198 function register name (first occurrence) register bits qty. 1st addr (hex) bei insertion enable dw_tx_ctl_bii_s0 (r/w) dw_txbei0_ins 4 0219c bei error insertion enable dw_tx_ctl_bii_s0 (r/w) dw_txbei0_errins 4 0219c bii byte insertion frame location dw_tx_ctl_bii_s0 (r/w) dw_txbii0_frm 4 0219c bii byte insertion row location dw_tx_ctl_bii_s0 (r/w) dw_txbii0_row 4 0219c
70 70 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) 8.1.5.3 sm backward defect indication (bdi) transmit bdi is inserted into the otu frame under the same conditions described in section 8.1.4, general defini- tion of bei, bdi, and iae insert and monitor, on page 66. if a bdi insertion condition occurs, software can program bdi to be inserted for twenty consecutive frames regardless of bdi conditions. table 35. transmit sm bdi insertion register summary function register name (first occurrence) register bits qty. 1st addr (hex) bdi failure interrupt alarm dw_alarm_s0 (w1c) dw_txbdi0_det_a 4 02020 bdi failure interrupt alarm mask dw_mask_s0 (r/w) dw_txbdi0_det_m 4 0205c bdi failure persistency dw_persist_2_s0 (ro) dw_txbdi0_det_p 4 02090 bdi failure state dw_state_2_s0 (ro) dw_txbdi0_det 4 020c0 bdi failure condition not detect when detect loc inhibit dw_tx_ctl_bdi0inh_2_s0 (r/w) dw_txbdi0_locinh 4 021a0 bdi failure condition not detect when detect oof inhibit dw_tx_ctl_bdi0inh_2_s0 (r/w) dw_txbdi0_oofinh 4 021a0 bdi failure condition not detect when detect lof inhibit dw_tx_ctl_bdi0inh_2_s0 (r/w) dw_txbdi0_lofinh 4 021a0 bdi failure condition not detect when detect los inhibit dw_tx_ctl_bdi0inh_2_s0 (r/w) dw_txbdi0_losinh 4 021a0 bdi failure condition not detect when detect sf inhibit dw_tx_ctl_bdi0inh_2_s0 (r/w) dw_txbdi0_sfinh 4 021a0 bdi failure condition not detect when detect sd inhibit dw_tx_ctl_bdi0inh_2_s0 (r/w) dw_txbdi0_sdinh 4 021a0 bdi failure condition not detect when detect ais inhibit dw_tx_ctl_bdi0inh_2_s0 (r/w) dw_txbdi0_aisinh 4 021a0 bdi failure condition not detect when detect oci inhibit dw_tx_ctl_bdi0inh_2_s0 (r/w) dw_txbdi0_ociinh 4 021a0 bdi failure condition not detect when detected fix pattern inhibit dw_tx_ctl_bdi0inh_2_s0 (r/w) dw_txbdi0_fixinh 4 021a0 bdi failure condition not detect after at least 20 frames inhibit dw_tx_ctl_bdi0inh_2_s0 (r/w) dw_txbdi0_timerinh 4 021a0 bdi detect inhibit dw_tx_ctl_bdi0inh_2_s0 (r/w) dw_txbdi0_inh 4 021a0 bdi insertion enable dw_tx_ctl_bdi0inh_2_s0 (r/w) dw_txbdi0_ins 4 021a0
agere systems inc. 71 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) 8.1.5.4 sm incoming alignment error overhead (iae) transmit iae is inserted into the otu frame under the same conditions described in section 8.1.4 on page 66. table 36. transmit iae insertion register summary function register name (first occurrence) register bits qty. 1st addr (hex) iae insertion enable dw_tx_ctl_top_v2_s0 (r/w) dw_txiae0_ins 4 02514 iae detect inhibit dw_tx_ctl_top_v2_s0 (r/w) dw_txiae0_inh 4 02514 iae insert inhibit due to rx lof condition dw_tx_ctl_top_v2_s0 (r/w) dw_txiae0_lofinh 4 02514 iae insert inhibit due to rx oof condition dw_tx_ctl_top_v2_s0 (r/w) dw_txiae0_oofinh 4 02514 iae failure interrupt alarm dw_alarm_v2_s0 (w1c) dw_txiae0_det_a 4 02030 iae failure interrupt alarm mask dw_mask_v2_s0 (r/w) dw_txiae0_det_m 4 0206c iae failure persistency dw_persist_v2_s0 (ro) dw_txiae0_det_p 4 020a0 iae failure state dw_state_v2_s0 (ro) dw_txiae0_det 4 020d0
72 72 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) 8.1.6 path monitoring insert (pm) the path monitoring bytes have identical functionality as the sm byte with (3-bit) stat available. these bytes will use the bip1 set of register bits (dw_txbip1_ins, etc.) in the insert control registers. 8.1.6.1 pm?bit interleaved parity (bip-8) the bip-8 byte is processed identically to the sm-bip8 byte (see section 8.1.5.1 on page 69). table 37. transmit pm bip byte insertion register summary 8.1.6.2 pm?backward error indication (bei) the bei bits are processed identically to the sm-bei bits (see section 8.1.5.2 on page 69). table 38. transmit pm bei insertion register summary function register name (first occurrence) register bits qty. 1st addr (hex) bip byte insertion enable dw_tx_ctl_bip_s0 (r/w) dw_txbip1_ins 4 02198 bip byte error insertion dw_tx_ctl_bip_s0 (r/w) dw_txbip1_errins 4 02198 bip byte insertion frame location dw_tx_ctl_bip_s0 (r/w) dw_txbip1_frm 4 02198 bip byte insertion row location dw_tx_ctl_bip_s0 (r/w) dw_txbip1_row 4 02198 function register name (first occurrence) register bits qty. 1st addr (hex) bei insertion enable dw_tx_ctl_bii_s0 (r/w) dw_txbei1_ins 4 0219c bei error insertion dw_tx_ctl_bii_s0 (r/w) dw_txbei1_errins 4 0219c bii byte insertion frame location dw_tx_ctl_bii_s0 (r/w) dw_txbii1_frm 4 0219c bii byte insertion row location dw_tx_ctl_bii_s0 (r/w) dw_txbii1_row 4 0219c
agere systems inc. 73 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) 8.1.6.3 pm?backward defect indication (bdi) the bdi bit is processed identically to the sm-bdi bit (see section 8.1.5.3 on page 70). table 39. transmit pm bdi insertion register summary function register name (first occurrence) register bits qty. 1st addr (hex) bdi failure interrupt alarm dw_alarm_s0 (w1c) dw_txbdi1_det_a 4 02020 bdi failure interrupt alarm mask dw_mask_s0 (r/w) dw_txbdi1_det_m 4 0205c bdi failure persistency dw_persist_2_s0 (ro) dw_txbdi1_det_p 4 02090 bdi failure state dw_state_2_s0 (ro) dw_txbdi1_det 4 020c0 bdi failure condition not detect when detect loc inhibit dw_tx_ctl_bdi1inh_v2_s0 (r/w) dw_txbdi1_locinh 4 02518 bdi failure condition not detect when detect oof inhibit dw_tx_ctl_bdi1inh_v2_s0 (r/w) dw_txbdi1_oofinh 4 02518 bdi failure condition not detect when detect lof inhibit dw_tx_ctl_bdi1inh_v2_s0 (r/w) dw_txbdi1_lofinh 4 02518 bdi failure condition not detect when detect los inhibit dw_tx_ctl_bdi1inh_v2_s0 (r/w) dw_txbdi1_losinh 4 02518 bdi failure condition not detect when detect sf inhibit dw_tx_ctl_bdi1inh_v2_s0 (r/w) dw_txbdi1_sfinh 4 02518 bdi failure condition not detect when detect sd inhibit dw_tx_ctl_bdi1inh_v2_s0 (r/w) dw_txbdi1_sdinh 4 02518 bdi failure condition not detect when detect ais inhibit dw_tx_ctl_bdi1inh_v2_s0 (r/w) dw_txbdi1_aisinh 4 02518 bdi failure condition not detect when detect oci inhibit dw_tx_ctl_bdi1inh_v2_s0 (r/w) dw_txbdi1_ociinh 4 02518 bdi failure condition not detect when detected fix pattern inhibit dw_tx_ctl_bdi1inh_v2_s0 (r/w) dw_txbdi1_fixinh 4 02518 bdi failure condition not detect after at least 20 frames inhibit dw_tx_ctl_bdi1inh_v2_s0 (r/w) dw_txbdi1_timerinh 4 02518 bdi detect inhibit dw_tx_ctl_bdi1inh_v2_s0 (r/w) dw_txbdi1_inh 4 02518 bdi insertion enable dw_tx_ctl_bdi1inh_v2_s0 (r/w) dw_txbdi1_ins 4 02518
74 74 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) 8.1.7 pm statistics the stat bits are set to 0x1 to indicate normal data signal and are overwritten under ais/oci and lck conditions. the generation of these maintenance signals is described in section 8.1.10 on page 76. table 40. transmit pm ais, oci, and lck insert register summary 8.1.8 tandem connection insert (tcmi) there are 6 tcm bytes in an otuk frame. the software can program any one of the tcm bytes to be processed in the transmit direction. the processing of the selected tcm bytes is identical to the pm bytes. these bytes will use the bip3 set of register bits (dw_txbip2_ins, etc.) in the insert control registers. 8.1.8.1 tcmi?bit interleaved parity (bip-8) the bip-8 byte is processed identically to the sm-bip8 byte (see section 8.1.5.1 on page 69). table 41. transmit tcm bip byte insertion register summary 8.1.8.2 tcmi?backward error indication (bei) the bei bits are processed identically to the sm-bei bits (see section 8.1.5.2 on page 69). table 42. transmit tcm bei insertion register summary function register name register bits qty. 1st addr (hex) stat 0x1 insert enable (if no error) dw_tx_ctl_top_v2_s0 (r/w) dw_txbii1_stat_ins 4 02514 function register name (first occurrence) register bits qty. 1st addr (hex) bip byte insertion enable dw_tx_ctl_bip_v2_s0 (r/w) dw_txbip2_ins 4 02524 bip byte error insertion dw_tx_ctl_bip_v2_s0 (r/w) dw_txbip2_errins 4 02524 bip byte insertion frame location dw_tx_ctl_bip_v2_s0 (r/w) dw_txbip2_frm 4 02524 bip byte insertion row location dw_tx_ctl_bip_v2_s0 (r/w) dw_txbip2_row 4 02524 function register name (first occurrence) register bits qty. 1st addr (hex) bei insertion enable dw_tx_ctl_bii_v2_s0 (r/w) dw_txbei2_ins 4 02520 bei error insertion dw_tx_ctl_bii_v2_s0 (r/w) dw_txbei2_errins 4 02520 bii byte insertion frame location dw_tx_ctl_bii_v2_s0 (r/w) dw_txbii2_frm 4 02520 bii byte insertion row location dw_tx_ctl_bii_v2_s0 (r/w) dw_txbii2_row 4 02520
agere systems inc. 75 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) 8.1.8.3 tcmi?backward defect indication (bdi) the bdi bit is processed identically to the sm-bdi bit (see section 8.1.5.3 on page 70). table 43. transmit tcm bdi insertion register summary function register name (first occurrence) register bits qty. 1st addr (hex) bdi failure interrupt alarm dw_alarm_s0 (w1c) dw_txbdi2_det_a 4 02020 bdi failure interrupt alarm mask dw_mask_s0 (r/w) dw_txbdi2_det_m 4 0205c bdi failure persistency dw_persist_2_s0 (ro) dw_txbdi2_det_p 4 02090 bdi failure state dw_state_2_s0 (ro) dw_txbdi2_det 4 020c0 bdi failure condition not detect when detect loc inhibit dw_tx_ctl_bdi2inh_v2_s0 (r/w) dw_txbdi2_locinh 4 0251c bdi failure condition not detect when detect oof inhibit dw_tx_ctl_bdi2inh_v2_s0 (r/w) dw_txbdi2_oofinh 4 0251c bdi failure condition not detect when detect lof inhibit dw_tx_ctl_bdi2inh_v2_s0 (r/w) dw_txbdi2_lofinh 4 0251c bdi failure condition not detect when detect los inhibit dw_tx_ctl_bdi2inh_v2_s0 (r/w) dw_txbdi2_losinh 4 0251c bdi failure condition not detect when detect sf inhibit dw_tx_ctl_bdi2inh_v2_s0 (r/w) dw_txbdi2_sfinh 4 0251c bdi failure condition not detect when detect sd inhibit dw_tx_ctl_bdi2inh_v2_s0 (r/w) dw_txbdi2_sdinh 4 0251c bdi failure condition not detect when detect ais inhibit dw_tx_ctl_bdi2inh_v2_s0 (r/w) dw_txbdi2_aisinh 4 0251c bdi failure condition not detect when detect oci inhibit dw_tx_ctl_bdi2inh_v2_s0 (r/w) dw_txbdi2_ociinh 4 0251c bdi failure condition not detect when detected fix pattern inhibit dw_tx_ctl_bdi2inh_v2_s0 (r/w) dw_txbdi2_fixinh 4 0251c bdi failure condition not detect after at least 20 frames inhibit dw_tx_ctl_bdi2inh_v2_s0 (r/w) dw_txbdi2_timerinh 4 0251c bdi detect inhibit dw_tx_ctl_bdi2inh_v2_s0 (r/w) dw_txbdi2_inh 4 0251c bdi insertion enable dw_tx_ctl_bdi2inh_v2_s0 (r/w) dw_txbdi2_ins 4 0251c
76 76 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) 8.1.9 tcm statistics the stat bits are set to 0x0 to indicate no tc signal and are overwritten under ais/oci and lck conditions. the generation of these maintenance signals is described in later sections. table 44. transmit tcm ais, oci, and lck insert register summary 8.1.10 alarm indication signal (ais), open connection indication (oci), locked (lck), and fixed pattern insert the macro automatically generates hardware ais in transmit direction insert when the alarms (i.e., loc, los, oof, or lof state bits) are active and the appropriate inhibit signals are inactive or software insert is active. the ais, oci, lck, or other pattern insert priority is defined in table 45. table 45. ais, oci, locked (lck), and fixed pattern insert priority note: see page 107 for description of dw_rxais_cond, dw_rxoci_cond, and dw_rxfix_cond. all frames are generated with a valid fec/dw framing pattern, otuk overhead, and the remaining frame bytes set to 0xff for ais insert, 0x66 for oci insert, or all fixed pattern (0x55?otuk-lck). at programmable mfas location bytes, overhead insert (such as dwac insert or oh0) in the otu oh field, is valid and is not overwritten by the ais generator. tcm0?tcm5, gcc0?gcc2, and aps/pcc inhibits are available. function register name (first occurrence) register bits qty. 1st addr (hex) stat 0x1 insert enable (if no error) dw_tx_ctl_top_v2_s0 (rw) dw_txbii2_stat_ins 4 02514 priority (highest = 1) ais, oci, or other pattern 1 ais insert (software) 2 oci insert (software) 3 fixed pattern insert (software) 4 ais insert (hardware) frm (tx) es (tx) or lb (rx to tx) (line_tx83loc and not (dw_txloc_aisinh)) or (frm_dw_txlos and not (dw_txlos_aisinh)) or (frm_dw_txoof and not (dw_txoof_aisinh)) or (frm_dw_txlof and not (dw_txlof_aisinh)) (line_tx83loc and not (dw_txloc_aisinh)) or (dw_rxais_cond and not (dw_txrxcond_aisinh)) 5 oci insert (hardware) (dw_rxoci_cond and not (dw_txrxcond_ociinh) 6 locked or fixed pattern insert (hardware) (dw_rxfix_cond and not (dw_txrxcond_fixinh))
agere systems inc. 77 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) the frame structures for ais, oci, and lck are shown below. figure 36. oduk-ais (tcmi, gcc1, gcc2, aps/pcc can be modified/monitored) figure 37. oduk-oci (tcmi, gcc1, gcc2, aps/pcc can be modified/monitored) figure 38. oduk-lck (tcmi, gcc1, gcc2, aps/pcc can be modified/monitored) figure 39 is an example of mfas, sm, ftfl, tcm2, gcc1, and gcc2 when inhibited during oduk-ais. example: dw_txoa12_pair = 0x2, dw_txoa12_mfas = 0x4, dw_rxais_ftflinh = 0x1, dw_rxais_gccinh = 0x6, dw_txais_tcminh = 0x2, and dw_txais_apsinh = 0x0. figure 39. oduk-ais (mfas, sm, ftfl, tcm2, gcc1, and gcc2 are inhibited) fa ch otu oh tcm6 tcm5 tcm4 tcm3 tcm2 tcm1 gcc1gcc2 aps/pcc ftfl overhead (0 to 15) payload (16 to 3823) 0xff fa ch otu oh tcm6 tcm5 tcm4 tcm3 tcm2 tcm1 gcc1gcc2 aps/pcc ftfl overhead (0 to 15) payload (16 to 3823) 0x66 fa ch otu oh tcm6 tcm5 tcm4 tcm3 tcm2 tcm1 gcc1gcc2 aps/pcc ftfl overhead (0 to 15) payload (16 to 3823) 0x55 fa oh oh tcm2 gcc1 gcc2 0xff overhead [0 to 15] payload [16 to 3823] ftfl fa oh oh tcm2 gcc1 gcc2 0xff overhead [0 to 15] payload [16 to 3823] ftfl
78 78 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) an ais signal is generated in case of a layer defect or an open connection. table 46. digital wrapper ais insert byte register summary function register name (first occurrence) register bits qty. 1st addr (hex) ais insertion enable. dw_tx_ctl_top_2_s0 (r/w) dw_txais_ins 4 02178 oci insertion enable. dw_tx_ctl_top_2_s0 (r/w) dw_txoci_ins 4 02178 fixed pattern byte insertion enable. dw_tx_ctl_top_2_s0 (r/w) dw_txfix_ins 4 02178 locked or fixed signal pattern to be inserted: 0 = locked. 1 = fixed. dw_tx_ctl_top_v2_s0 (r/w) dw_txlck_fix 4 02514 fixed pattern byte: 0x00 = open connection indication/all 0s. 0xff = layer defect/all 1s (default). dw_tx_ctl_ais_2_s0 (r/w) dw_txfix_val 4 02194 number of multiframe (mfas) bytes after oa2 (see table 25 on page 57). dw_tx_ctl_oa12_pat_s0 (r/w) dw_txoa12_mfas 4 02180 loss-of-clock ais inhibit. when set to logic 1, the ais insert is inhibited in case of loss-of-clock (line_tx83loc). dw_tx_ctl_ais_2_s0 (r/w) dw_txloc_aisinh 4 02194 out-of-frame ais inhibit. when set to logic 1, the ais insert is inhibited in case of out-of-frame (frm_txoof). dw_tx_ctl_ais_2_s0 (r/w) dw_txoof_aisinh 4 02194 loss-of-frame ais inhibit. when set to logic 1, the ais insert is inhibited in case of loss-of-frame (frm_txlof). dw_tx_ctl_ais_2_s0 (r/w) dw_txlof_aisinh 4 02194 loss-of-signal ais inhibit. when set to logic 1, the ais insert is inhibited in case of loss-of-signal (frm_txlos). dw_tx_ctl_ais_2_s0 (r/w) dw_txlos_aisinh 4 02194 receive ais condition inhibit. dw_tx_ctl_ais_2_s0 (r/w) dw_txrxcond_aisinh 4 02194 receive oci condition inhibit. dw_tx_ctl_ais_2_s0 (r/w) dw_txrxcond_ociinh 4 02194 receive other fixed pattern condition inhibit. dw_tx_ctl_ais_2_s0 (r/w) dw_txrxcond_fixinh 4 02194 ftfl inhibit during ais. dw_tx_ctl_ais_v2_s0 (r/w) dw_txais_ftflinh 4 02528 inhibit tcm0?tcm5 overwritten by ais/oci/lck 1 . 1. if tcm insert during ais/oci/lck, stat [2:0] will be inserted 001 for normal operation mode. (iae in-use is not available.) dw_tx_ctl_ais_v2_s0 (r/w) dw_txais_tcminh 4 02528 inhibit gcc0?gcc2 overwritten by ais/oci/lck. dw_tx_ctl_ais_v2_s0 (r/w) dw_txais_gccinh 4 02528 inhibit aps/pcc inhibit overwritten by ais/oci/lck. dw_tx_ctl_ais_v2_s0 (r/w) dw_txais_apsinh 4 02528 inhibit tcm0?tcm5 overwritten by ais/oci/lck 1 inhibit. dw_tx_ctl_ais_v2_s0 (r/w) dw_txais_tcmstat_ iaeinh 402514
agere systems inc. 79 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) 8.1.11 dwac insert four insert digital wrapper access channels (dwac) are provided on chip along with four drop dwacs. these channels provide most of the monitoring and insert capabilities for the fec/dw overhead bytes. the insert dwac consists of four signals per channel (total of four dwac channels): ? output clock at ~10.455 mhz (10 gbits/s mode (slice 0 only) and quad 2.5 gbits/s mode). ? output superframe sync (~326.7/~81.68 khz?10 gbits/s (fec/dw), ~81.68/~20.42 khz?quad 2.5 gbits/s (fec/dw)) coincident with the msb (most significant bit) in quad 2.5 gbits/s mode, or msn (most significant nibble) in 10 gbits/s mode of the first byte in frame 0. the sync pulse is provided on the rising edge of dwac clock. at mfas = 0x00, sync pulse is set high for two clock cycles. ? input data: 4 bits (a nibble) in 10 gbits/s mode and 1 bit per stream in quad 2.5 gbits/s mode. ? input insert enable signal: active-high signal coincident with the first two msb[7:6] of the byte to insert in quad 2.5 gbits/s mode or coincident with the two msns in 10 gbits/s mode. see table 28 on page 61. all the dwac bytes insertion control is described below. the data stream format from the device is identical to figure 33 on page 66. note: see the timing characteristics section in the hardware design guide for the transmit transport overhead access channel sec tion. figure 40. transmit dwac frame definition table 47. dwac byte insertion control dwac enable data value description dwac_dw_txdata_en[3:0]/[0] sampled at [msb], [msb ? 1]/[msn], [msn ? 1] positions only. 11 insert data from the serial dwac input. 00 default standards. 01/10 passthrough (if enabled, otherwise default standard is inserted). oh1 oh2 oh3 oh4 oh5 oh6 oh7 oh8 oh9 oh10 oh11 oh12 oh13 oh14 oh15 oh16 [7:0] data enable sync transmitted serially or nibble wide. dw_dwac_txsync dw_dwac_txclko dwac_dw_txdata[3:0] dwac_dw_txdata_en[0] oh1 [6] oh1 [3:0] oh1 [7] oh1 [7:4]
80 80 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) table 48. transmit dwac insertion register summary 8.1.12 prbs insert and monitor a pseudorandom sequence (prbs: 2 29 ? 1 or 2 31 ? 1) data can be inserted into payload locations (exclude over- head and check bits locations). when the pseudorandom sequence is inserted, a 2 29 ? 1 or a 2 31 ? 1 sequence is used in the payload data bytes with the pattern starting after each of the overhead bytes. in addition, all overhead bytes function normally. the pseudorandom pattern uses either a 2 29 ? 1 (536, 870, 911 bits), or a 2 31 ? 1 (2, 147, 483, 647 bits) pattern length specified in o.150. the 2 29 ? 1 sequence is generated by a 29-stage shift register whose twenty-seventh and twenty-ninth stage outputs are added and fed back to the first stage. the output of the last stage can be inverted (which yields a sequence with up to 29 zeros). the 2 31 ? 1 sequence is generated by a 31-stage shift reg- ister whose twenty-eighth and thirty-first stage outputs are added and fed back to the first stage. the output of the last stage can be inverted (which yields a sequence with up to 31 zeros). in quad 2.5 gbits/s mode, the prbs macro generates four independent 32-bit pn sequences. in 10 gbits/s mode, all 128 bits are generated as one pn sequence. the prbs pattern can be inverted by setting a single control bit. only the slice 0 control bit is valid in 10 gbits/s mode. a single-bit error can be inserted. the prbs generator injects a single error bit at the msb in the test pat- tern. the most significant bit (msb) of each slice is inverted. for example, in quad 2.5 gbits/s, the 127th (slice 3), 95th (slice 2), 64th (slice 1), and 31th (slice 0) are used. in 10 gbits/s mode, only the 127th is used. table 49. prbs insert control bit register summary function register name (first occurrence) register bits qty. 1st addr (hex) dwac byte insertion enable dw_dwac_tx_ctl_s0 (r/w) dwac_txins 4 021c4 function register name (first occurrence) register bits qty. 1st addr (hex) transmit prbs pattern (payload only) insertion enable dw_tx_ctl_top_2_s0 (r/w) dw_txprbs_ins 4 02178 transmit prbs pattern sequence selection: 0 = 2 29 ? 1 1 = 2 31 ? 1 dw_prbs_ctl_s0 (r/w) dw_txprbs_29_31_pat 4 021e0 transmit prbs inverted pattern (payload only) insertion enable dw_prbs_ctl_s0 (r/w) dw_txprbs_inv 4 021e0 transmit prbs error insert bit (1 error bit per 128 bits in 10 gbits/s mode, and 1 bit per 32 bits in 2.5 gbits/s mode) dw_prbs_ctl_s0 (r/w) dw_txprbs_1berrins 4 021e0
agere systems inc. 81 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) prbs data in payload locations (exclude overhead and check bytes location) can be monitored by the prbs mon- itor at the input pins. a pseudorandom sequence pattern (either 2 31 ? 1 or 2 29 ? 1) can be detected. when 32 consecutive bits match the pattern, the pattern sync state declares itself in-sync. if eight or more consec- utive mismatches are in the payload sequence, the corresponding pattern sync state declares itself out-of-sync. in 10 gbits/s mode, the payload goes into sync if the most up-to-date 32 bits (lsb) are matched, and declares out-of-sync if the most up-to-date of the last 32 bits (lsb) has eight or more consecutive mismatches in the pay- load sequence. note: if 32 bits match and/or eight mismatches occur in less up-to-date patterns [127:32], sync state will be ignored. the pattern sync state also provides an interrupt alarm and persistency. the prbs can also monitor for an inverted pattern via the microprocessor. any bit error occurring after the monitor is in the in-sync state is reported by an 8-bit counter. this counter (dw_txprbs_ecnt) will contain the number of bit errors (clear-on-read toggle from the microprocessor). table 50. prbs monitor register summary function register name (first occurrence) register bits qty. 1st addr (hex) transmit prbs monitor pattern (payload only) monitor is expected to be inverted when set dw_prbs_ctl_v2_s0 (rw) dw_txprbs_mon_inv 4 02530 transmit prbs monitor pattern sequence selection: 0 = 2 29 ? 1 1 = 2 31 ? 1 dw_prbs_ctl_v2_s0 (rw) dw_txprbs_mon_29_ 31_pat 4 02530 monitored prbs pattern sync interrupt alarm bit dw_alarm_v2_s0 (w1c) dw_txprbs_sync_a 4 02030 monitored prbs pattern sync mask bit dw_mask_v2_s0 (rw) dw_txprbs_sync_m 4 0206c monitored prbs pattern sync persistency bit dw_persist_v2_s0 (ro) dw_txprbs_sync_p 4 020a0 when the prbs pattern (payload only) detects 32 matches in a row, it declares itself in-sync and the error detector is enabled. if the device detects eight consecutive mismatches, the test pattern detector declares itself out-of-sync and starts searching again. 0 = in-sync. 1 = out-of-sync. dw_state_v2_s0 (ro) dw_txprbs_sync 4 020d0 monitored prbs error pattern counter. the prbs monitor counts the number of times the input data differs from the expected value in an 8-bit counter that holds its count when it reaches the maximum value of 255. this counter is reset when ready by the microproces- sor, and is not affected by the pmrst signal (clear-on-read). dw_tx_cnt_prbs_ v2_s0 (cor) dw_txprbs_ecnt 4 02604
82 82 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8 digital wrapper insert (continued) 8.1 functional description of digital wrapper insert (continued) 8.1.13 digital wrapper check byte insert the check bits location can be set to pass through its value by setting a control bit. otherwise, all check bits are set to zero. check byte passthrough is not available when the transmit data is generated from the transmit elastic store. table 51. dw insert check byte insertion register summary 9 strong fec supermacro reed-solomon (rs) encoder 9.1 functional description of rs encoder the rs encoder calculates and inserts check bytes which are remainders after polynomial division of the payload by generating polynomial, g(z) = (z + 1) (z + a 1 )...(z+a 15 ), where a is a root of the binary primitive polynomial x 8 +x 4 +x 3 +x 2 +1. data arrives to the rs encoder grouped as four slices of 32 bits. each slice has four independent check byte calcu- lators. each calculator accepts 239 bytes of payload data followed by 16 bytes of all-zeros data, and generates 16 bytes of check data. the check bytes replace all 16 incoming zero bytes unless the rs encoder is in bypass mode. table 52. rs encoder register summary function register name (first occurrence) register bits qty. 1st addr (hex) transmit check bits location zero insertion: 0 = check bits are set to zero 1 = check bits pass through. dw_tx_ctl_top_2_s0 (r/w) dw_tx_cbpass 4 02178 transmit no fix stuff enable (10 gbits/s dw mode only) i.e., 119th of 0?254 columns is reserved for a stuff column dw_tx_ctl_top_v2_s0 (rw) dw_tx_no_fs 4 02514 function register name (first occurrence) register bits qty. 1st addr (hex) rs encoder mode control: 0 = normal. 1 = bypass. rs_tx_ctl_top_s0 (r/w) rs_tx_enc 4 0221a
agere systems inc. 83 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 10 strong fec supermacro scrambler 10.1 functional description of strong fec supermacro scrambler the scrambler optionally scrambles incoming data. the scrambling sequence can be selected between two differ- ent polynomials: x 7 + x + 1 and x 16 +x 12 +x 3 +x+1. when scrambling is enabled, the whole fec/dw frame is scrambled, with the exception of the framing byte, by a selected polynomial (x 7 +x+1 or x 16 +x 12 +x 3 + x + 1). scrambling is initiated at each frame on the first bit which follows the framing byte. the first bit sequence of the scrambler is all 1s. figure 41. x 7 + x + 1 frame synchronous scrambler (g.975) figure 42. x 16 +x 12 +x 3 + x + 1 frame synchronous scrambler (g.709) table 53. scrambler register summary function register name (first occurrence) register bits qty. 1st addr (hex) scrambling control: 0 = off. 1 = on. rs_tx_ctl_top_s0 (r/w) rs_tx_scr 4 0221a scrambling sequence select: 0 = 7-bit (x 7 +x+1). 1 = 16-bit (x 16 +x 12 +x 3 +x+1). rs_tx_ctl_top_s0 (r/w) rs_tx_scr_7_16_pol 4 0221a d q data in clock x 7 + x + 1 scrambled d q d q d q d q d q d q data out d q clock d q d q d q data in x 16 + x 12 + x 3 + x + 1 scrambled d q d q d q d q d q data out
84 84 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 11 strong fec supermacro error insert 11.1 functional description of error insert the error insert inserts various types of errors for rs code testing. for each slice, an error insert block accepts 32 bits of data. there is a total of four slices instantiated to make the 128-bit wide data for 16-way and 64-way 10 gbits/s mode. a 32-bit mask register corresponds to the 32-bit wide data bus for the error insertion. when the mask bit is set to logic 1, the corresponding data bit is inverted. the number of skipping clock cycles can be programmed through the microprocessor. error bits combining with the number of skipping clock cycles can be repeated by using a con- trol bit bus. the first column of error can be chosen via the microprocessor. the stream of errors start when there is a 0 ? 1 transition. see figure 43, example of error insert setup diagram, on page 85. ensure the inserted error bits are within the range as noted in table 54. table 54. error insert register summary function register name (first occurrence) register bits qty. 1st addr (hex) mask for the error insertion on the 32-bit data bus rs_tx_ctl_errmsk1_s0/ rs_tx_ctl_errmsk0_s0 (r/w) rs_txerr1_mask/ rs_txerr0_mask 4 02226/ 02227 number of skipping clock cycles between 32-bit error pattern rs_tx_ctl_errskip_s0 (r/w) rs_txerr_skip 4 0221e number of repeating clock cycles between 32-bit error pattern rs_tx_ctl_errrept_s0 (r/w) rs_txerr_repeat 4 02222 start column (note: in 162.5g mode, 0?1019; 1610g mode, 0?254; 6410g mode, 0?1019. out of range values default to 0.) rs_tx_ctl_errcol_s0 (r/w) rs_txerr_col 4 0222f error start control bit rs_tx_ctl_top_s0 (r/w) rs_txerr_start 4 0221a error insert finish alarm rs_alarm_s0 (w1c) rs_txerr_a 4 02028 error insert finish mask rs_mask_2_s0 (r/w) rs_txerr_m 4 02064 error insert finish state rs_state_s0 (ro) rs_txerr 4 020c8
agere systems inc. 85 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 11 strong fec supermacro error insert (continued) 11.1 functional description of error insert (continued) figure 43. example of error insert setup diagram example: rs_txerr_skip[7:0] = 02 rs_txerr_repeat[9:0] = 04 rs_txerr_col[11:0] = 04 rs_txerr1_mask = 00 rs_txerr0_mask = 00065 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ... 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 . . . 27 28 29 30 31 rs_txerr_start column (clock cycle) bit position (0 = lsb, 31 = msb)
86 86 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 12 interleaver 12.1 functional description of interleaver the rs encoder performs interleaving of code blocks in order to enhance the immunity of a transmission system to burst errors, in byte manner. in 10 gbits/s mode, all four interleavers work in synchronization. the read/write addresses of slice 1, slice 2, and slice 3 are synchronized with slice 0, which is a master slice. 13 deinterleaver 13.1 functional description of deinterleaver the rs decoder performs deinterleaving of code blocks in order to enhance the immunity of the transmission sys- tem to burst errors, in byte manner. in 10 gbits/s mode, all four deinterleavers work in synchronization. the read/write addresses of slice 1, slice 2, and slice 3 are synchronized with slice 0, which is a master slice. 14 framer receive direction requirements the framer functionality of the receive direction is identical to the transmit direction in section 7, strong fec supermacro fec/dw framer (los, oof, lof), on page 55. table 55. los register summary function register name (first occurrence) register bits qty. 1st addr (hex) los detect time threshold frm_rx_ctl_losdet_s0 (r/w) frm_rxlos_det 4 022a0 los interrupt alarm frm_alarm_s0 (w1c) frm_rxlos_a 4 0202c los alarm mask frm_mask_s0 (r/w) frm_rxlos_m 4 02068 los persistency frm_persist_s0 (ro) frm_rxlos_p 4 0209c los state frm_state_s0 (ro) frm_rxlos 4 020cc
agere systems inc. 87 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 14 framer receive direction requirements (continued) table 56. framer register summary function register name (first occurrence) register bits qty. 1st addr (hex) framer disable frm_rx_ctl_oof_3_s0 (r/w) frm_rx_disable 4 022ac oa1 frame byte value frm_rx_ctl_oa12_s0 (r/w) frm_rxoa1_val 4 022a4 oa2 frame byte value frm_rx_ctl_oa12_s0 (r/w) frm_rxoa2_val 4 022a4 number of repeat oa1 byte (same as oa2): 0 = one oa1?s, one oa2?s 7 = eight oa1?s, eight oa2?s see table 25 on page 57 frm_rx_ctl_oa12_pat_3_s0 (r/w) frm_rxoa12_pairs 4 022a8 number of framing pattern pairs (oa1/oa2) used to transition between out-of-frame to in-frame state (oof, 1 ? 0) frm_rx_ctl_oa12_pat_3_s0 (r/w) frm_rxoa12_pairclr 4 022a8 number of framing pattern pairs (oa1/oa2) used to transition between in-frame to out-of-frame state (oof, 0 ? 1) frm_rx_ctl_oa12_pat_3_s0 (r/w) frm_rxoa12_pairset 4 022a8 out-of-frame set frm_rx_ctl_oof_3_s0 (r/w) frm_rxoof_set 4 022ac out-of-frame clear frm_rx_ctl_oof_3_s0 (r/w) frm_rxoof_clr 4 022ac out-of-frame interrupt alarm frm_alarm_s0 (w1c) frm_rxoof_a 4 0202c out-of-frame interrupt alarm mask frm_mask_s0 (r/w) frm_rxoof_m 4 02068 out-of-frame persistency frm_persist_s0 (ro) frm_rxoof_p 4 0209c out-of-frame state frm_state_s0 (ro) frm_rxoof 4 020cc
88 88 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 14 framer receive direction requirements (continued) table 57. loss-of-frame control register summary 15 strong fec supermacro descrambler 15.1 functional description of descrambler the descrambler optionally descrambles incoming data. the scrambling sequence can be selected between two different polynomials: x 7 +x+1 or x 16 +x 12 +x 3 +x+1. once descrambling is requested, the whole fec/dw frame is descrambled, with the exception of the framing byte, by a selected polynomial initiated at each frame on the first bit which follows the framing byte. the first bit sequence of the descrambler is all ones. table 58. descrambler register summary function register name (first occurrence) register bits qty. 1st addr (hex) loss-of-frame set frm_rx_ctl_lof_2_s0 (r/w) frm_rxlof_set 4 022b0 loss-of-frame clear frm_rx_ctl_lof_2_s0 (r/w) frm_rxlof_clr 4 022b0 loss-of-frame interrupt alarm frm_alarm_s0 (w1c) frm_rxlof_a 4 0202c loss-of-frame interrupt alarm mask frm_mask_s0 (r/w) frm_rxlof_m 4 02068 loss-of-frame persistency frm_persist_s0 (ro) frm_rxlof_p 4 0209c loss-of-frame state frm_state_s0 (ro) frm_rxlof 4 020cc function register name (first occurrence) register bits qty. 1st addr (hex) rx descrambling control: 0 = off. 1 = on. rs_rx_ctl_top_s0 (r/w) rs_rx_dscr 4 02200 rx descrambling sequence select: 0 = 7-bit (x 7 +x+1). 1 = 16-bit (x 16 +x 12 +x 3 +x+1). rs_rx_ctl_top_s0 (r/w) rs_rx_dscr_7_16_pol 4 02200
agere systems inc. 89 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 16 reed-solomon (rs) decoder 16.1 functional description of rs decoder the rs decoder detects and corrects transmission errors, and calculates and reports incoming ber based on the exact number of corrected bits. when the fec/dw framer is in the oof, lof, or los state, the associated decoder is disabled. 16.1.1 error detect and correct data arrives to the rs decoder grouped as four slices of 32 bits. each slice has four independent error detect-and-correct blocks. each block accepts 8-bit wide rs code blocks, and outputs 8-bit wide corrected code blocks. the number of corrected bits and the number of uncorrectable blocks are counted and reported to the ber monitor block, per slice. if uncorrectable errors are detected, correction operation is turned off automatically on a block-by-block basis and the number of corrected bit errors is not counted. there are four operational decoding modes monitor shutdown decode only correct when the rs decoder is set to the monitoring mode, the error is detected and monitored, but data is not corrected without delay. when set to shut-down mode, the decoding function is disabled and data is bypassed without delay. when set to decode-only mode, the error is detected and monitored, but data is not corrected with delay. when set to correct mode, the error is detected and corrected. the transition between decode-only and correct are hitless. table 59. rs decoder register summary 16.1.2 ber monitor the reed solomon statistics count correctable errors that are detected and corrected in the rs decoder. the mon- itoring of the line ber before correction can be done through the knowledge of the exact number of corrected bits. the errors that remain uncorrected after forward error correction can be considered negligible in the computation of ber, for low error rates. function register name (first occurrence) register bits qty. 1st addr (hex) rs decoder mode control rs_rx_ctl_top_s0 (r/w) rs_rx_dec 4 02200
90 90 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 16 reed-solomon (rs) decoder (continued) 16.1 functional description of rs decoder (continued) 16.1.3 error count the corrected bits and the uncorrectable blocks are accumulated per slice in 16-bit saturating counters based on either bit or block errors. in bit mode, each corrected error (or uncorrectable block) causes the counter to incre- ment. if block error is selected, each fec/dw frame which has a corrected error (or uncorrectable block) causes the counter to increment by only one. the counter stops at the maximum value and will not roll over, and is cleared by the pmrst signal. table 60. rs error register summary 16.1.3.1 ber detecting and reporting the corrected errors are used to detect sf and sd conditions. the ber threshold for each defect is separately provisionable for each slice over a range of 1 x 10 ?n values, where n = 3 to 9. the detection times and error limits used to detect and clear both defects are dependent on the provisioned ber threshold, as shown in table 61. the values shown in table 61 are the powerup defaults and are dependent on the mode selected (2.5 gbits/s or 16-way/64-way 10 gbits/s). these values can be changed through the correspond- ing registers and are common to all slices. the clearing ber threshold for each defect is always one-tenth of the detection threshold. as can be seen in table 61, the range of possible detect threshold are 1 x 10 ?3 to 1 x 10 ?9 , which results in clear thresholds of 1x10 ?4 to 1 x 10 ?10 . for example, to detect sd at 1 x 10 ?5 ber in 2.5 gbits/s mode, the detection time is 3.2 ms and the detect error limit is 83. the clearing would take place at 1 x 10 ?6 ber, with a clearing time of 51.2 ms and a clearing error limit of 665. figure 44 on page 91 illustrates sd detection and clearing using the default values. function register name (first occurrence) register bits qty. 1st addr (hex) rs error count control rs_rx_ctl_top_s0 (r/w) rs_err_bitblk 4 02200 rs rx 0 ? 1 corrected bit counter rs_rx_cnt_0to1_errbit0_s0/ rs_rx_cnt_0to1_errbit1_s0 (ro) rs_rx_err00_0to1_bitcnt/ rs_rx_err01_0to1_bitcnt 4 0254a/ 0254b rs rx 1 ? 0 corrected bit counter rs_rx_cnt_1to0_errbit0_s0/ rs_rx_cnt_1to0_errbit1_s0 (ro) rs_rx_err0_1to0_bitcnt/ rs_rx_err1_1to0_bitcnt 4 02553/ 02554 rs rx corrected bit counter rs_rx_cnt_errbit0_s0/ rs_rx_cnt_errbit1_s0 (ro) rs_rx_err0_bitcnt/ rs_rx_err1_bitcnt 4 0234c/ 0234d rs rx uncorrectable block counter rs_rx_cnt_errblk0_s0/ rs_rx_cnt_errblk1_s0 (ro) rs_rx_unc0_blkcnt/ rs_rx_unc1_blkcnt 4 02355/ 02356
agere systems inc. 91 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 16 reed-solomon (rs) decoder (continued) 16.1 functional description of rs decoder (continued) table 61. ber threshold time and error limits for line sd and sf detection figure 44. example of sd detection (10 ?5 ber) and clearing (10 ?6 ber) in 10 gbits/s mode, the thresholds are compared against the sum of the four slice sf and sd counts. a detected sf or sd defect causes a corresponding maskable interrupt status bit to be set. the sd/sf ber control bits select the bit error rate for a particular slice. these control bits then select the detec- tion time, the detect error limit, and the clear error limits for each slice. the detect error limit and the clear error limit registers contain 16-bit values, while the detection time registers use the lower 15 bits for a value and the upper bit for a time unit specifier. for the detection time register, the value contained in the lower 15 bits is either specified in 0.1 ms units (upper bit = 0) or in 0.1 s units (upper bit = 1). note that the receive sync pulse is used as the timing reference. provisioned ber threshold detection time detect error limit clear error limit 2.5 gbits/s 10 gbits/s 2.5 gbits/s 10 gbits/s 2.5 gbits/s 10 gbits/s 1 10 ?3 0.4 ms 0.1 ms 1044 1044 ? ? 1 10 ?4 0.4 ms 0.1 ms 104 104 520 520 1 10 ?5 3.2 ms 0.8 ms 83 83 415 415 1 10 ?6 51.2 ms 10.3 ms 133 133 665 665 1 10 ?7 409.6 ms 102.4 ms 106 106 530 530 1 10 ?8 3200 ms 800 ms 85 85 425 425 1 10 ?9 52.4 s 10.6 s 136 136 680 680 1 10 ?10 419.4 s 104.8 s ? ? 545 545 sd accumulated bit errors time (ms) 665 83 3.2 8 6 57.2 108.4 sd detected sd cleared sd detection window sd clearing window
92 92 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 16 reed-solomon (rs) decoder (continued) 16.1 functional description of rs decoder (continued) a fixed windowing scheme is used for sd/sf detection. the window size is determined by the value in the detec- tion time register for the specified bit error rate. an sd or sf alarm is declared immediately when the accumulated error count exceeds the value specified in the detect error limit register. if this error limit is not reached by the end of the window, then the accumulated error count is reset to zero. when an sd or sf alarm is declared, the accumulated error count resets and clearing begins using the bit error rate threshold that is one-tenth of the specified value, along with the corresponding detection time registers. clearing of the sd or sf alarm only occurs at the end of the window when the accumulated error count is less than the value specified in the clear error limit register. the rs decoder reports current ber so the customer knows which is a current ber. for this, seven bers are monitored at the same time. once a certain level ber is detected, lower-level bers are ignored and the high- est-level of ber is reported as a current ber, i.e., when 1 x 10 ?4 ber is detected, bers from 1 x 10 ?5 to 1 x 10 ?9 are ignored and 1 x 10 ?4 is reported as a current ber. figure 45. rs decoder block diagram 10 -9 ber monitor current ber detect ber comparator sd detect sd threshold current ber sf threshold sf detect corrected bits ber comparator 10 -8 ber monitor 10 -7 ber monitor 10 -6 ber monitor 10 -5 ber monitor 10 -4 ber monitor 10 -3 ber monitor
agere systems inc. 93 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 16 reed-solomon (rs) decoder (continued) 16.1 functional description of rs decoder (continued) table 62. rs register summary function register name (first occurrence) register bits qty. 1st addr (hex) rs sd threshold select rs_rx_ctl_top_s0 (r/w) rs_rxber_sd_ threshold 4 02200 rs sf threshold select rs_rx_ctl_top_s0 (r/w) rs_rxber_sf_ threshold 4 02200 rs sd detect interrupt alarm rs_alarm_s0 (w1c) rs_rxber_sd_det_a 4 02028 rs sf detect interrupt alarm rs_alarm_s0 (w1c) rs_rxber_sf_det_a 4 02028 rs sd detect mask rs_mask_2_s0 (r/w) rs_rxber_sd_det_m 4 02064 rs sf detect mask rs_mask_2_s0 (r/w) rs_rxber_sf_det_m 4 02064 rs sd detect persistence rs_persist_s0 (ro) rs_rxber_sd_det_p 4 02098 rs sf detect persistence rs_persist_s0 (ro) rs_rxber_sf_det_p 4 02098 rs sd detect state rs_state_s0 (ro) rs_rxber_sd_det 4 020c8 rs sf detect state rs_state_s0 (ro) rs_rxber_sf_det 4 020c8 rs ber report rs_rx_cnt_berrep_s0 (ro) rs_rxber_report 4 0235e rs ber-3 detection time rs_rx_ctl_berdt0 (r/w) rs_rxber_dettime0 1 02204 rs ber-4 detection time rs_rx_ctl_berdt1 (r/w) rs_rxber_dettime1 1 02205 rs ber-5 detection time rs_rx_ctl_berdt2 (r/w) rs_rxber_dettime2 1 02206 rs ber-6 detection time rs_rx_ctl_berdt3 (r/w) rs_rxber_dettime3 1 02207 rs ber-7 detection time rs_rx_ctl_berdt4 (r/w) rs_rxber_dettime4 1 02208 rs ber-8 detection time rs_rx_ctl_berdt5 (r/w) rs_rxber_dettime5 1 02209 rs ber-9 detection time rs_rx_ctl_berdt6 (r/w) rs_rxber_dettime6 1 0220a rs ber-10 detection time rs_rx_ctl_berdt7 (r/w) rs_rxber_dettime7 1 0220b rs ber-3 detect error limit rs_rx_ctl_berset0 (r/w) rs_rxber_set0 1 0220c rs ber-4 detect error limit rs_rx_ctl_berset1 (r/w) rs_rxber_set1 1 0220e rs ber-5 detect error limit rs_rx_ctl_berset2 (r/w) rs_rxber_set2 1 02210 rs ber-6 detect error limit rs_rx_ctl_berset3 (r/w) rs_rxber_set3 1 02212 rs ber-7 detect error limit rs_rx_ctl_berset4 (r/w) rs_rxber_set4 1 02214 rs ber-8 detect error limit rs_rx_ctl_berset5 (r/w) rs_rxber_set5 1 02216 rs ber-9 detect error limit rs_rx_ctl_berset6 (r/w) rs_rxber_set6 1 02218 rs ber-4 clear error limit rs_rx_ctl_berclr0 (r/w) rs_rxber_clr0 1 0220d rs ber-5 clear error limit rs_rx_ctl_berclr1 (r/w) rs_rxber_clr1 1 0220f rs ber-6 clear error limit rs_rx_ctl_berclr2 (r/w) rs_rxber_clr2 1 02211 rs ber-7 clear error limit rs_rx_ctl_berclr3 (r/w) rs_rxber_clr3 1 02213 rs ber-8 clear error limit rs_rx_ctl_berclr4 (r/w) rs_rxber_clr4 1 02215 rs ber-9 clear error limit rs_rx_ctl_berclr5 (r/w) rs_rxber_clr5 1 02217 rs ber-10 clear error limit rs_rx_ctl_berclr6 (r/w) rs_rxber_clr6 1 02219
94 94 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17 digital wrapper drop 17.1 functional description of digital wrapper drop the digital wrapper drop is used for overhead monitoring after the rs decoder (checkbyte calculate and correct). for each slice, the digital wrapper drop block accepts 32 bits of data. there is a total of four slices instantiated to create a 128-bit wide block for 16-way and 64-way 10 gbits/s mode. all fec/dw frame overhead dropping and monitoring functions supported by the dw in the receive direction are summarized in the following list: ? internal fec overhead bytes monitor. ? bip-8 monitor (also has an available tcm byte). ? bii monitor, bdi detect, iae detect, and bei monitor (also has an available tcm byte). ? ais, oci, or other fixed pattern detect (stat monitor in tcmi and pm bytes). ? dwac drop. ? insertion of ais, oci, or other fixed pattern. ? prbs monitor (also provides insert). all monitors are disabled if the receive direction, loss-of-signal, loss-of-clock, and out-of-frame alarms are disabled. in the loss-of-frame case, the monitor continues functioning if its associate ais inhibit is set. whenever the continuous n-times detect (cntd) signals are defined, they require not only that the monitored sig- nal be consistent for n consecutive frames, but also that the frame bytes be error free for all n frames before the status can be updated. n can range from 1 to 15. programming a cntd block with a value of 0 turns off the cntd detection. in the receive direction, 128-bit input data will be retimed and passed through without any processing to either dw_es_rxdata[127:0] or dwfec_sys_rx83data[127:0]. (note that ais insertion may need to be inhibited.) in a loopback mode, the 128-bit input data can be selected from dw_rs_txdata[127:0]. 17.1.1 internal fec overhead bytes monitor (oh0 to oh3) there are up to four overhead bytes per fec or dw frame which can be detected and reported via the micropro- cessor. the provisioning location is programmable and operates identically to the digital wrapper oh0 to oh3 insert. see section 8.1, functional description of digital wrapper insert, on page 61 for the programming example. the monitored overhead byte is updated via a microprocessor after n consecutive consistent occurrences (frames) of a new pattern overhead byte is received. they can be grouped as the following: ? four 1-byte monitors. ? two 2-byte monitors. ? one 3-byte and one 1-byte monitor. ? one 4-byte monitor. multiple bytes do not need to be contiguous. four bytes can be inserted from internal register per stream. table 63. oh0?oh3 monitor byte group indication summary any changes to the receive overhead byte state must be reported to its interrupt alarm and persistency register bit. the interrupt alarm mask bit is also provided. control bits dw_rxoh0123_grp[1:0] description valid cntd control value 00 four 1-byte group oh3, oh2, oh1, oh0 01 two 2-byte groups oh2, oh0 10 one 1-byte and one 3-byte group oh1, oh0 11 one 4-byte group oh0
agere systems inc. 95 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) table 64. internal fec overhead byte monitor register summary function register name (first occurrence) register bits qty. 1st addr (hex) overhead byte monitor group indi- cation: 00 = four 1-byte. 01 = two 2-byte. 10 = one 1-byte and one 3-byte. 11 = one 4-byte. dw_rx_ctl_top_s0 (r/w) dw_rxoh0123_grp 4 02150 overhead byte monitor interrupt alarm. dw_alarm_s0 (w1c) dw_rxoh0_det_a 4 02020 overhead byte monitor interrupt alarm mask. dw_mask_s0 (r/w) dw_rxoh0_det_m 4 0205c overhead byte monitor value. dw_rx_val_oh01_s0 (ro) dw_rxoh0_val 4 02320 continuous n-times detect for receive overhead byte (oh0). (the valid range for this register is 0x1?0xf. 0x0 is used to turn off the monitor.) dw_rx_ctl_oh0_2_s0 (r/w) dw_rxoh0_cntd 4 02154 overhead byte monitor frame location (dw mode only). dw_rx_ctl_oh0_2_s0 (r/w) dw_rxoh0_frm 4 02154 overhead byte monitor row loca- tion. dw_rx_ctl_oh0_2_s0 (r/w) dw_rxoh0_row 4 02154 overhead byte monitor interrupt alarm. dw_alarm_s0 (w1c) dw_rxoh1_det_a 4 02020 overhead byte monitor interrupt alarm mask. dw_mask_s0 (r/w) dw_rxoh1_det_m 4 0205c overhead byte monitor value. dw_rx_val_oh01_s0 (ro) dw_rxoh1_val 4 02320 continuous n-times detect for receive overhead byte (oh1). (the valid range for this register is 0x1?0xf. 0x0 is used to turn off the monitor.) dw_rx_ctl_oh1_2_s0 (r/w) dw_rxoh1_cntd 4 02158 overhead byte monitor frame location (dw mode only). dw_rx_ctl_oh1_2_s0 (r/w) dw_rxoh1_frm 4 02158 overhead byte monitor row loca- tion. dw_rx_ctl_oh1_2_s0 (r/w) dw_rxoh1_row 4 02158 overhead byte monitor interrupt alarm. dw_alarm_s0 (w1c) dw_rxoh2_det_a 4 02020 overhead byte monitor interrupt alarm mask. dw_mask_s0 (r/w) dw_rxoh2_det_m 4 0205c overhead byte monitor value. dw_rx_val_oh23_s0 (ro) dw_rxoh2_val 4 02324
96 96 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17.1.2 bip-8 monitor (see figure 32 on page 65) for each fec or dw frame, up to three single bip-8 bytes per slice, even parity, is computed over the i ? 2 frame (overhead and check bytes). in every fec or dw frame, the received bip-8 value is extracted and compared to the calculated bip-8 byte for the previous frame. three per-slice bip-8 bytes? locations for monitoring are programmable. in fec frame, only the row location is used. errors in the bip-8 code are tabulated in an internal 27-bit counter based on either bit or block errors, as pro- visioned for each slice through the bip-8 mode control bit. in bit mode (selected by default), each bip-8 bit in error causes the counter to increment. if block error is selected, each bip-8 code in error causes the counter to increment only once. regardless of which mode is selected, the value in the counter is transferred to maintenance register on the rising edge of the performance monitoring clock, at which point the counter is cleared. the counter will stop at the maximum value and will not roll over. twelve bip-8 monitoring blocks are implemented, corresponding to each slice. in quad 2.5 gbits/s mode, all these blocks function independently on 32 bits of data. in 10 gbits/s mode, the slice 0 block functions on 128 bits of data and the other blocks are disabled. continuous n-times detect for receive overhead byte (oh2). (the valid range for this register is 0x1?0xf. 0x0 is used to turn-off the monitor.) dw_rx_ctl_oh2_2_s0 (r/w) dw_rxoh2_cntd 4 0215c overhead byte monitor frame location (dw mode only). dw_rx_ctl_oh2_2_s0 (r/w) dw_rxoh2_frm 4 0215c overhead byte monitor row loca- tion. dw_rx_ctl_oh2_2_s0 (r/w) dw_rxoh2_row 4 0215c overhead byte monitor interrupt alarm. dw_alarm_s0 (w1c) dw_rxoh3_det_a 4 02020 overhead byte monitor interrupt alarm mask. dw_mask_s0 (r/w) dw_rxoh3_det_m 4 0205c overhead byte monitor value. dw_rx_val_oh23_s0 (ro) dw_rxoh3_val 4 02324 continuous n-times detect for receive overhead byte (oh3). (the valid range for this register is 0x1?0xf. 0x0 is used to turn off the monitor.) dw_rx_ctl_oh3_2_s0 (r/w) dw_rxoh3_cntd 4 02160 overhead byte monitor frame location (dw mode only). dw_rx_ctl_oh3_2_s0 (r/w) dw_rxoh3_frm 4 02160 overhead byte monitor row loca- tion. dw_rx_ctl_oh3_2_s0 (r/w) dw_rxoh3_row 4 02160 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) table 64. internal fec overhead byte monitor register summary (continued) function register name (first occurrence) register bits qty. 1st addr (hex)
agere systems inc. 97 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) 17.1.3 bii monitor?bdi detect and bei monitor bdi can be detected via microprocessor control. there are 3 bdi bits per slice, for a total of 12 bits of bdi indica- tion bytes, which can be detected by specifying the location of the frame and the row. in fec frame mode, only the row location is used. see figure 33 on page 66 for bei and bdi locations in the bii byte. bei (bip error per frame) will be accumulated in a counter. bdi bit detect is declared when the monitored bdi bit is set after a number of n consecutive consistent occurrences (frames). three sets of bii byte can be monitored. 17.1.4 otu section monitoring (sm) the following subfields in the sm bytes are monitored. these bytes will use the bip0 set of register bits (dw_rxbip0_disable, etc.) in the monitor control registers. 17.1.4.1 sm?bip-8 the bip-8 is computed over all the bytes of opuk (overhead and payload) in the nth frame and is compared against the received bip in the n + 2 frame. the bip errors (if any) are reported to the transmit overhead processor for insertion of bei in the corresponding transmit sm byte. these bit errors are also accumulated in an internal reg- ister. the content of this internal register is transferred to the corresponding reporting register on performance monitoring reset. the internal accumulating register is then cleared. the internal accumulating counter can be set to count the number of bits (0x0) or blocks (0x1) in error. table 65. sm bip-8 monitor register summary function register name (first occurrence) register bits qty. 1st addr (hex) bip calculation disable. dw_rx_ctl_top_s0 (r/w) dw_rxbip0_disable 4 02150 bip byte counter mode: 0 = bit count mode. 1 = block count mode. dw_rx_ctl_bip_s0 (r/w) dw_rxbip0_bit_blk 4 0216c bip byte monitor frame location (dw mode only): 00 = frame n. 01 = frame n + 1. 10 = frame n + 2. 11 = frame n + 3. dw_rx_ctl_bip_s0 (r/w) dw_rxbip0_frm 4 0216c bip monitor byte row location. dw_rx_ctl_bip_s0 (r/w) dw_rxbip0_row 4 0216c dw bip-8 error counter. dw_rx_cnt_bip00_s0/ dw_rx_cnt_bip01_s0 (ro) dw_rxbip00_ecnt/ dw_rxbip01_ecnt 4 02328/ 02329
98 98 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) 17.1.4.2 sm?backward error indication (bei) these bits indicate the bip errors in the far end and are accumulated in an internal register. the content of this internal register is transferred to the corresponding reporting register on performance monitoring reset. the internal accumulating register is then cleared. the internal accumulating counter can be set to count the number of bits (0x0) or blocks (0x1) in error. table 66. sm bei monitor register summary 17.1.4.3 sm?backward defect indication (bdi) this bit is captured in the corresponding register. a new value is only validated after it has been received for a pro- grammable n consecutive frames. table 67. sm bdi monitor register summary function register name (first occurrence) register bits qty. 1st addr (hex) bei calculation disable. dw_rx_ctl_top_s0 (r/w) dw_rxbei0_disable 4 02150 bei counter mode: 0 = bit count mode. 1 = block count mode. dw_rx_ctl_bii_s0 (r/w) dw_rxbei0_bit_blk 4 02170 bii byte monitor frame location (dw mode only): 00 = frame n. 01 = frame n + 1. 10 = frame n + 2. 11 = frame n + 3. dw_rx_ctl_bii_s0 (r/w) dw_rxbii0_frm 4 02170 bii monitor byte row location. dw_rx_ctl_bii_s0 (r/w) dw_rxbii0_row 4 02170 dw bei error counter. dw_rx_cnt_bei00_s0/ dw_rx_cnt_bei01_s0 (ro) dw_rxbei00_ecnt/ dw_rxbei01_ecnt 4 0233a/ 0233b function register name (first occurrence) register bits qty. 1st addr (hex) bdi bit monitor interrupt alarm. dw_alarm_s0 (w1c) dw_rxbdi0_det_a 4 02020 bdi bit monitor interrupt alarm mask. dw_mask_s0 (r/w) dw_rxbdi0_det_m 4 0205c bdi bit monitor persistency. dw_persist_2_s0 (ro) dw_rxbdi0_det_p 4 02090 bdi bit monitor state. dw_state_2_s0 (ro) dw_rxbdi0_det 4 020c0 continuous n-times detect and clear bdi monitor byte detect condition. (the valid range for this register is 0x1?0xf. 0x0 is used to turn off the monitor.) dw_rx_ctl_biicntd_s0 (r/w) dw_rxbdi0_cntd 4 02174
agere systems inc. 99 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) 17.1.4.4 sm?incoming alignment error (iae) this bit indicates the alignment error in the far end and is captured in the corresponding register. a new value is only validated after it has been received for a programmable n consecutive frames. the bit location for the iae value is fixed in the sm byte at row 0, column 9, bit 2. table 68. sm iae monitor register summary 17.1.5 odu path monitoring (pm) the pm bytes are processed identically to the sm/tcm byte (see section 7.1.4 on page 60). these bytes will use the bip1 set of register bits (dw_rxbip1_disable, etc.) in the monitor control registers. 17.1.5.1 pm?bip-8 table 69. pm bip-8 monitor register summary function register name (first occurrence) register bits qty. 1st addr (hex) iae bit monitor interrupt alarm dw_alarm_v2_s0 (w1c) dw_rxiae0_det_a 4 02030 iae bit monitor interrupt alarm mask dw_mask_v2_s0 (r/w) dw_rxiae0_det_m 4 0206c iae bit monitor persistency dw_persist_v2_s0 (ro) dw_rxiae0_det_p 4 020a0 iae bit monitor state dw_state_v2_s0 (ro) dw_rxiae0_det 4 020d0 continuous n-times detect and clear iae monitor byte detect condition (the valid range for this register is 0x1?0xf. 0x0 is used to turn off the monitor.) dw_rx_ctl_v2_s0 (r/w) dw_rxiae0_cntd 4 02500 function register name (first occurrence) register bits qty. 1st addr (hex) bip calculation disable dw_rx_ctl_top_s0 (r/w) dw_rxbip1_disable 4 02150 bip byte counter mode: 0 = bit count mode. 1 = block count mode. dw_rx_ctl_bip_s0 (r/w) dw_rxbip1_bit_blk 4 0216c bip byte monitor frame location (dw mode only): 00 = frame n. 01 = frame n + 1. 10 = frame n + 2. 11 = frame n + 3. dw_rx_ctl_bip_s0 (r/w) dw_rxbip1_frm 4 0216c bip monitor byte row location dw_rx_ctl_bip_s0 (r/w) dw_rxbip1_row 4 0216c dw bip-8 error counter dw_rx_cnt_bip10_s0/ dw_rx_cnt_bip11_s0 (ro) dw_rxbip10_ecnt/ dw_rxbip11_ecnt 4 02331/ 02332
100 100 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) 17.1.5.2 pm?backward error indication (bei) table 70. pm bei monitor register summary 17.1.5.3 pm?backward defect indication (bdi) table 71. pm bdi monitor register summary function register name (first occurrence) register bits qty. 1st addr (hex) bei calculation disable dw_rx_ctl_top_s0 (r/w) dw_rxbei1_disable 4 02150 bei counter mode: 0 = bit count mode. 1 = block count mode. dw_rx_ctl_bii_s0 (r/w) dw_rxbei1_bit_blk 4 02170 bii byte monitor frame location (dw mode only): 00 = frame n. 01 = frame n + 1. 10 = frame n + 2. 11 = frame n + 3. dw_rx_ctl_bii_s0 (r/w) dw_rxbii1_frm 4 02170 bii monitor byte row location dw_rx_ctl_bii_s0 (r/w) dw_rxbii1_row 4 02170 dw bei error counter dw_rx_cnt_bei10_s0/ dw_rx_cnt_bei11_s0 (ro)/ dw_rxbei10_ecnt/ dw_rxbei11_ecnt 4 02343/ 02344 function register name (first occurrence) register bits qty. 1st addr (hex) bdi bit monitor interrupt alarm. dw_alarm_s0 (w1c) dw_rxbdi1_det_a 4 02020 bdi bit monitor interrupt alarm mask. dw_mask_s0 (r/w) dw_rxbdi1_det_m 4 0205c bdi bit monitor persistency. dw_persist_2_s0 (ro) dw_rxbdi1_det_p 4 02090 bdi bit monitor state. dw_state_2_s0 (ro) dw_rxbdi1_det 4 020c0 continuous n-times detect and clear bdi monitor byte detect condition. (the valid range for this register is 0x1?0xf. 0x0 is used to turn off the monitor.) dw_rx_ctl_biicntd_s0 (r/w) dw_rxbdi1_cntd 4 02174
agere systems inc. 101 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) 17.1.5.4 pm?status (stat) table 72. stat bits monitoring ais, oci, or other fixed patterns can be detected via microprocessor control. one indication byte can be detected by specifying the frame location, row location, and expected value. in fec frame mode, only the row location is used. the ais, oci, or other pattern byte detect is declared when the monitored byte is ais (all 1s), oci (all 6s), or other fixed pattern byte pattern after setting a number of n consecutive consistent occurrences (frames). the ais, oci, or other pattern byte detect is cleared when the monitored byte is found to be a mismatch from ais (all 1s), oci (all 6s), or other pattern byte for a clearing number of n consecutive consistent occurrences (frames). ais, oci, or other pattern byte detects report the interrupt alarm, persistency, and state bit via the microprocessor. ms value maintenance signal 0x66 oduk-oci 0x55 oduk-lck 0xff oduk-ais
102 102 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) table 73. pm stat register summary function register name (first occurrence) register bits qty. 1st addr (hex) ais monitor byte detect condition interrupt alarm dw_alarm_s0 (w1c) dw_rxais_det_a 4 02020 ais monitor byte detect condition interrupt alarm mask dw_mask_s0 (r/w) dw_rxais_det_m 4 0205c ais monitor byte detect condition persistence dw_persist_2_s0 (ro) dw_rxais_det_p 4 02090 ais monitor byte detect condition state dw_state_2_s0 (ro) dw_rxais_det 1 4 020c0 oci monitor byte detect condition interrupt alarm dw_alarm_s0 (w1c) dw_rxoci_det_a 4 02020 oci monitor byte detect condition interrupt alarm mask dw_mask_s0 (r/w) dw_rxoci_det_m 4 0205c oci monitor byte detect condition persistence dw_persist_2_s0 (ro) dw_rxoci_det_p 4 02090 oci monitor byte detect condition state dw_state_2_s0 (ro) dw_rxoci_det 2 4 020c0 fix monitor byte detect condition interrupt alarm dw_alarm_s0 (w1c) dw_rxfix_det_a 4 02020 fix monitor byte detect condition interrupt alarm mask dw_mask_s0 (r/w) dw_rxfix_det_m 4 0205c fix monitor byte detect condition persistence dw_persist_2_s0 (ro) dw_rxfix_det_p 4 02090 fix monitor byte detect condition state dw_state_2_s0 (ro) dw_rxfix_det 3 4 020c0 fixed pattern monitor and insert byte value dw_rx_ctl_aisbyte_s0 (r/w) dw_rxfix_val 4 02168 continuous n-times detect for setting ais, oci, or other fixed pattern monitor byte detect condition. (the valid range for this register is 0x1?0xf. 0x0 is used to turn off the monitor.) dw_rx_ctl_ais_2_s0 (r/w) dw_rxais_setcntd 4 02164 1. dw_rxais_det is when ais byte or pm-stat or tcm-stat detected ais. 2. dw_rxoci_det is when ais byte or pm-stat or tcm-stat detected oci. 3. dw_rxfix_det is when ais byte or pm-stat or tcm-stat detected lck or fixed pattern is detected.
agere systems inc. 103 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface continuous n-times detect for clearing ais, oci, or other fixed pattern monitor byte detect condition. (the valid range for this register is 0x1?0xf. 0x0 is used to turn off the monitor.) dw_rx_ctl_ais_2_s0 (r/w) dw_rxais_clrcntd 4 02164 ais, oci, or other fixed pattern byte monitor frame location (dw mode only): 00 = frame n. 01 = frame n + 1. 10 = frame n + 2. 11 = frame n + 3. dw_rx_ctl_ais_2_s0 (r/w) dw_rxais_frm 4 02164 ais, oci, or other fixed pattern monitor byte row location dw_rx_ctl_ais_2_s0 (r/w) dw_rxais_row 4 02164 stat n-time dw_rx_ctl_oh_v2_s0 (rw) dw_rxbii1_stat_cntd 4 02504 new validated stat value interrupt alarm dw_alarm_v2_s0 (ro) dw_rx_bii1_stat_new_a 4 02030 new validated stat value persistency mask dw_mask_v2_s0 (ro) dw_rx_bii1_stat_new_m 4 0206c new validated stat value persistency dw_persist_v2_s0 (ro) dw_rx_bii1_stat_new_p 4 020a0 stat value dw_rx_mon_v2_s0 (ro) dw_rx_bii1_stat 4 02546 1. dw_rxais_det is when ais byte or pm-stat or tcm-stat detected ais. 2. dw_rxoci_det is when ais byte or pm-stat or tcm-stat detected oci. 3. dw_rxfix_det is when ais byte or pm-stat or tcm-stat detected lck or fixed pattern is detected. 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) table 73. pm stat register summary (continued) function register name (first occurrence) register bits qty. 1st addr (hex)
104 104 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) 17.1.6 oduk tandem connection monitoring (tcm) there are 6 tcm bytes in an otu frame. any one of these 6 tcm bytes can be monitored by selecting it via the microprocessor. the selected tcm bytes are then processed identically to the sm byte (section 7.1.4 on page 60). these bytes will use the bip2 set of register bits (dw_rxbip2_disable, etc.) in the monitor control registers 17.1.6.1 tcmi?bip-8 table 74. tcm bip-8 monitor register summary 17.1.6.2 tcmi?backward error indication (bei) table 75. tcm bei monitor register summary function register name (first occurrence) register bits qty. 1st addr (hex) bip calculation disable dw_rx_ctl_v2_s0 (r/w) dw_rx_bip2_disable 4 02500 bip byte counter mode: 0 = bit count mode. 1 = block count mode. dw_rx_ctl_v2_s0 (r/w) dw_rx_bip2_bit_blk 4 02500 bip byte monitor frame location (dw mode only): 00 = frame n. 01 = frame n + 1. 10 = frame n + 2. 11 = frame n + 3. dw_rx_ctl_bii2_v2_2_s0 (r/w) dw_rxbip2_frm 4 02508 bip monitor byte row location dw_rx_ctl_bii2_v2_2_s0 (r/w) dw_rxbip2_row 4 02508 dw bip-8 error counter dw_rx_cnt_bip20_v2_s0/ dw_rx_cnt_bip21_v2_s0 (ro) dw_rxbip20_ecnt/ dw_rxbip21_ecnt 4 02534/ 02535 function register name (first occurrence) register bits qty. 1st addr (hex) bei calculation disable dw_rx_ctl_v2_s0 (r/w) dw_rx_bei2_disable 4 02500 bei counter mode: 0 = bit count mode. 1 = block count mode. dw_rx_ctl_v2_s0 (r/w) dw_rx_bei2_bit_blk 4 02500 bii byte monitor frame location (dw mode only): 00 = frame n. 01 = frame n + 1. 10 = frame n + 2. 11 = frame n + 3. dw_rx_ctl_bii2_v2_2_s0 (r/w) used for bei, bdi, and stat locations dw_rxbii2_frm 4 02508 bii monitor byte row location dw_rx_ctl_bii2_v2_2_s0 (r/w) used for bei, bdi, and stat locations dw_rxbii2_row 4 02508 dw bei error counter dw_rx_cnt_bei20_v2_s0/ dw_rx_cnt_bei21_v2_s0 (ro) dw_rxbei20_ecnt/ dw_rxbei21_ecnt 4 0253d/ 0253e
agere systems inc. 105 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) 17.1.6.3 tcmi?backward defect indication (bdi) table 76. tcm bdi monitor register summary 17.1.6.4 status (stat) table 77. stat bits monitoring table 78. tcm stat register summary function register name (first occurrence) register bits qty. 1st addr (hex) bdi bit monitor interrupt alarm dw_alarm_v2_s0 (w1c) dw_rxbdi2_det_a 4 02030 bdi bit monitor interrupt alarm mask dw_mask_v2_s0 (r/w) dw_rxbdi2_det_m 4 0206c bdi bit monitor persistency dw_persist_v2_s0 (ro) dw_rxbdi2_det_p 4 020a0 bdi bit monitor state dw_state_v2_s0 (ro) dw_rxbdi2_det 4 020d0 continuous n-times detect and clear bdi monitor byte detect condition (the valid range for this register is 0x1?0xf. 0x0 is used to turn off the monitor.) dw_rx_ctl_cntd_v2_s0 (r/w) dw_rxbdi2_cntd 4 02510 ms value maintenance signal 0x66 oduk-oci 0x55 oduk-lck 0xff oduk-ais function register name register bits qty. 1st addr (hex) stat n-time dw_rx_ctl_cntd_v2_s0 (rw) dw_rxbii2_stat_cntd 4 02510 new validated stat value interrupt alarm dw_alarm_v2_s0 (ro) dw_rx_bii2_stat_new_a 4 02030 new validated stat value persistency mask dw_mask_v2_s0 (ro) dw_rx_bii2_stat_new_m 4 0206c new validated stat value persistency dw_persist_v2_s0 (ro) dw_rx_bii2_stat_new_p 4 020a0 stat value dw_rx_mon_v2_s0 (ro) dw_rx_bii2_stat 4 02546
106 106 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) 17.1.7 dwac drop the drop dwac consists of the following three signals per channel (total of four dwac channels): ? output clock at ~10.455 mhz (10 gbits/s mode and quad 2.5 gbits/s mode). ? output superframe sync (~326.7/~81.68 khz?10 gbits/s (fec/dw), ~81.68/~20.42 khz?quad 2.5 gbits/s (fec/dw)) coincident with the msb (most significant bit) of the first byte in frame 0. ? output data: 4 bits in 10 gbits/s mode and 1 bit per stream in quad 2.5 gbits/s mode. note: see the timing characteristics section in the hardware design guide for the transmit transport overhead access channel sec tion. dw_dwac_rxclko is not 50% duty cycle. figure 46. receive dwac frame definition three bii bytes can be overwritten to bii byte locations using monitored bip-8 error per frame and dw_txbdi_det information (signal from transmit direction). the bii overwritten byte capability is provided for a regenerator mode. table 79. receive dwac drop register summary note: bdi/bei/iae value are calculated, processed, and overwritten at the corresponding location. ex., bei calculated value can be inserted at sm-bei before being dropped by the dwac. function register name (first occurrence) register bits qty. 1st addr (hex) bdi (tx detect) overwritten to dwac drop (sm-bdi) dw_dwac_rx_ctl_s0 (r/w) dwac_rxbdi0_ovwr 4 021c0 bei (tx detect) overwritten to dwac drop (sm-bei) dw_dwac_rx_ctl_s0 (r/w) dwac_rxbei0_ovwr 4 021c0 iae (tx detect) overwritten to dwac drop (sm-iae) dw_dwac_rx_ctl_v2_s0 (r/w) dwac_rxiae0_ovwr 4 0252c bdi (tx detect) overwritten to dwac drop (pm-bdi) dw_dwac_rx_ctl_s0 (r/w) dwac_rxbdi1_ovwr 4 021c0 bei (tx detect) overwritten to dwac drop (pm-bei) dw_dwac_rx_ctl_s0 (r/w) dwac_rxbei1_ovwr 4 021c0 bdi (tx detect) overwritten to dwac drop (tcm-bdi) dw_dwac_rx_ctl_v2_s0 (r/w) dwac_rxbdi2_ovwr 4 0252c bei (tx detect) overwritten to dwac drop (tcm-bei) dw_dwac_rx_ctl_v2_s0 (r/w) dwac_rxbei2_ovwr 4 0252c oh1 oh2 oh3 oh4 oh5 oh6 oh7 oh8 oh9 oh10 oh11 oh12 oh13 oh14 oh15 oh16 [7:0] data enable sync transmitted serially or nibble wide. dw_dwac_rxsync dw_dwac_rxclko dwac_dw_rxdata[3:0] oh1 [6] oh1 [3:0] oh1 [7] oh1 [7:4]
agere systems inc. 107 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) 17.1.8 insertion of ais, oci, and other fixed patterns the macro will automatically generate ais, oci, and other fixed pattern bytes with valid framing byte patterns by alarms (hardware) or software insert. the ais, oci, or other pattern insert priorities are defined in table 23 on page 54. table 80. ais, oci, and fixed pattern insert priority dw_rxais_cond is active-high (output) if ais pattern in stat1 or stat2 is detected and inserted. dw_rxoci_cond is active-high (output) if oci pattern in stat1 or stat2 is detected. dw_rxfix_cond is active-high (output) if fixed or lck pattern in stat1 or stat2 is detected. when dw_rxais_cond is set to logic 1, a default pattern of all 1s will be inserted. when the dw_rxoci_det alarm is in detect mode (active), an oci (0x66) pattern will be inserted. when the dw_rxfix_det alarm is detected, all lck (0x55) or fixed patterns in dw_rxfix_val will be inserted via the microprocessor. ais, oci, or other fixed patterns can be inserted. ais/oci/lock signals are generated as per table 77 on page 105. the dw_rxais_cond is also an output to an elastic store (rx). at programmable mfas location bytes, over- head in the otu oh field is valid and is not overwritten by ais generator. tcm0?tcm5, gcc0?gcc2, and aps/pcc inhibit are available. in 10 gbits/s mode, only slice 0 is valid. priority (highest = 1, lowest = 6) ais, oci, or other pattern 1 ais insert (software) (dw_rxais_ins) 2 oci insert (software) (dw_rxoci_ins) 3 lck or fixed pattern insert (software) (dw_rxfix_ins) 4 ais alarm detect (hardware) (line_rx83loc and not (dw_rxloc_aisinh)) or (frm_dw_rx_los and not (dw_rxlos_aisinh)) or (frm_dw_rx_oof and not (dw_rxoof_aisinh)) or (frm_dw_rx_lof and not (dw_rxlof_aisinh)) or (rs_ber_sd and not (dw_rxsd_aisinh)) or (rs_ber_sd and not (dw_rxsd_aisinh)) or (dw_rxais_det 1 ) and not (dw_rxais_detinh) 1. dw_rxais_det is when ais byte or pm-stat or tcm-stat detected ais. 5 oci alarm detect (hardware) (dw_rxoci_det 2 and not (dw_rxoci_detinh)) 2. dw_rxoci_det is when ais byte or pm-stat or tcm-stat detected oci. 6 other fixed pattern alarm detect (hardware) (dw_rxfix_det 3 and not (dw_rxfix_detinh)) 3. dw_rxfix_det is when ais byte or pm-stat or tcm-stat detected lck or fixed pattern is detected.
108 108 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) table 81. insertion of ais register summary function register name (first occurrence) register bits qty. 1st addr (hex) ais insert control bit (when set to logic 1, ais condition will be inserted) dw_rx_ctl_top_s0 (r/w) dw_rxais_ins 4 02150 oci insert control bit. dw_rx_ctl_top_s0 (r/w) dw_rxoci_ins 4 02150 fixed pattern insert control bit dw_rx_ctl_top_s0 (r/w) dw_rxfix_ins 4 02150 number of multiframe (mfas) bytes after oa2 (see table 25 on page 57) dw_rx_ctl_oh_v2_s0 (r/w) dw_rxoa12_mfas 4 02504 loss-of-clock ais inhibit (when set to logic 1, the ais insert will be inhibited in case of loss-of-clock (line_rx83loc)) dw_rx_ctl_top_s0 (r/w) dw_rxloc_aisinh 4 02150 out-of-frame ais inhibit (when set to logic 1, the ais insert will be inhibited in case of out-of-frame (frm_rxoof)) dw_rx_ctl_top_s0 (r/w) dw_rxoof_aisinh 4 02150 loss-of-frame ais inhibit (when set to logic 1, the ais insert will be inhibited in case of loss-of-frame (frm_rxlof)) dw_rx_ctl_top_s0 (r/w) dw_rxlof_aisinh 4 02150 loss-of-signal ais inhibit (when set to logic 1, the ais insert will be inhibited in case of loss-of-signal (frm_rxlos)) dw_rx_ctl_top_s0 (r/w) dw_rxlos_aisinh 4 02150 ais failure condition when detect sf inhibit dw_rx_ctl_ais_v2_s0 (r/w) dw_rxsf_aisinh 4 0250c ais failure condition when detect sd inhibit dw_rx_ctl_ais_v2_s0 (r/w) dw_rxsd_aisinh 4 0250c ais detect, ais pattern insert inhibit dw_rx_ctl_top_s0 (r/w) dw_rxais_detinh 4 02150 oci detect, oci pattern insert inhibit dw_rx_ctl_top_s0 (r/w) dw_rxoci_detinh 4 02150 fixed pattern detect, fixed pattern insert inhibit dw_rx_ctl_top_s0 (r/w) dw_rxfix_detinh 4 02150 choose insert pattern of lck (0x55) or fix value dw_rx_ctl_v2_s0 (rw) dw_rxlck_fix 4 02500 ftfl inhibit during ais dw_rx_ctl_ais_v2_s0 (rw) dw_rxais_ftflinh 4 0250c
agere systems inc. 109 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface the following figure shows the alarm structure of the ais/oci/fix detection and insertion. figure 47. ais/oci/fix alarm structure (per slice) tcm0 to tcm5 insert during ais/oci/lck 1 dw_rx_ctl_ais_v2_s0 (rw) dw_rxais_tcminh 4 0250c gcc0 to gcc2 inhibit during ais/oci/lck dw_rx_ctl_ais_v2_s0 (rw) dw_rxais_gccinh 4 0250c aps/pcc inhibit during ais/oci/lck dw_rx_ctl_ais_v2_s0 (rw) dw_rxais_apsinh 4 0250c tcm0 to tcm5 insert during ais/oci/lck 1 inhibit dw_rx_ctl_oh_v2_s0 (rw) dw_rxais_tcmstat_iaeinh 4 02504 1. if tcm insert during ais/oci/lck, stat [2:0] will be inserted 001 for normal operation mode. (iae in-use is not available.) 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) table 81. insertion of ais register summary (continued) function register name (first occurrence) register bits qty. 1st addr (hex) ais_cntd_det ais_stat1 (pmais) ais_stat1 (tcmais) dw_rxais_inh sys_rx83loc dw_rxloc_aisinh frm_dw_rx_los dw_rxlos_aisinh frm_dw_rx_lof dw_rxlof_aisinh frm_dw_rx_oof dw_rxoof_aisinh rs_sf dw_rxsf_aisinh rs_sd dw_rxsd_aisinh dw_rxais_det dw_rxais_ins dw_rxais_cond oci_cntd_det oci_stat1 (pmais) oci_stat1 (tcmais) dw_rxoci_inh dw_rxoci_det (oci pattern insert) dw_rxoci_ins dw_rxoci_cond (ais pattern insert) fix_cntd_det fix_stat1 (pmais) fix_stat1 (tcmais) dw_rxfix_inh dw_rxfix_det (fix pattern insert) dw_rxfix_ins dw_rxfix_cond
110 110 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) 17.1.9 prbs monitor prbs data in payload locations (excluding overhead and check bytes location) can be monitored by the prbs monitor at the output pins (dw_rxprbsdata[127:0] and dw_rxprbsdata_en[3:0]). a pseudorandom sequence pattern (either 2 31 ? 1 or 2 29 ? 1) can be detected. when 32 consecutive bits matches in its pattern, the pattern sync state declares itself in-sync. if eight or more con- secutive mismatches are in the payload sequence, the corresponding pattern sync state declares itself out-of-sync. in 10 gbits/s mode, the payload goes into sync if the most up-to-date 32 bits (lsb) are a match, and declares itself out-of-sync if the most up-to-date of the last 32 bits (lsb) has eight or more consecutive mismatches in the pay- load sequence. note: if 32 bits match and/or eight mismatches occur in a less up-to-date pattern [127:32], it will be ignored. the pattern sync state also provides interrupt alarm and persistence. the prbs can also monitor for inverted pat- terns via the microprocessor. for any bit errors occurring after the monitor is in the in-sync state, an 8-bit counter reports the number of bit errors using clear-on-read toggle from the microprocessor. table 82. prbs monitor register summary function register name (first occurrence) register bits qty. 1st addr (hex) receive prbs pattern (payload only) moni- tor is expected to be inverted when set dw_prbs_ctl_s0 (r/w) dw_rxprbs_inv 4 021e0 receive prbs pattern sequence selection: 0 = 2 29 ? 1. 1 = 2 31 ? 1. dw_prbs_ctl_s0 (r/w) dw_rxprbs_29_31_pat 4 021e0 receive prbs error pattern counter. the prbs monitor counts the number of times the input data differs from the expected value in an 8-bit counter that holds its count when it reaches the maximum value of 255. this counter is reset when ready by the microprocessor, and is not affected by the pmrst signal. (clear-on-read) dw_rx_cnt_ prbs_s0 (cor) dw_rxprbs_ecnt 4 02600 receive prbs pattern sync interrupt alarm bit dw_prbs_ alarm_s0 (w1c) dw_rxprbs_sync_a 4 02024 receive prbs pattern sync mask bit dw_prbs_mask_ s0 (r/w) dw_rxprbs_sync_m 4 02060 receive prbs pattern sync persistency bit dw_prbs_ persist_s0 (ro) dw_rxprbs_sync_p 4 02094 receive prbs pattern sync alarm bit dw_prbs_ alarm_s0 (w1c) dw_rxprbs_sync 4 02024 when the prbs pattern (payload only) detects 32 matches in a row, it declares itself in-sync and the error detector is enabled. if the device detects eight consecutive mis- matches, the test pattern detector declares itself out-of-sync and starts searching again. 0 = in-sync. 1 = out-of-sync. dw_prbs_state_ s0 (ro) dw_rxprbs_sync 4 020c4
agere systems inc. 111 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 17 digital wrapper drop (continued) 17.1 functional description of digital wrapper drop (continued) 17.1.10 prbs insert table 83. prbs insert register summary 17.1.11 no fix stuff mode a register bit can be enabled to disable the fix stuff column. table 84. receive data no fix stuff mode register summary function register name (first occurrence) register bits qty. 1st addr (hex) prbs pattern (payload only) insert dw_prbs_ctl_v2_s0 (r/w) dw_rxprbs_ins 4 02530 prbs inverted pattern insert (payload only) insert dw_prbs_ctl_v2_s0 (r/w) dw_rxprbs_ins_inv 4 02530 prbs pattern sequence insert selection: 0 = 2 29 ? 1 1 = 2 31 ? 1 dw_prbs_ctl_v2_s0 (r/w) dw_rxprbs_ins_29_31_pat 4 02530 received prbs error insert bit (1 error bit per 128 bits in 10 gbits/s mode, and 1 bit per 32 bits in 2.5 gbits/s mode) dw_prbs_ctl_v2_s0 (r/w) dw_rxprbs_ins_1berrins 4 02530 function register name (first occurrence) register bits qty. 1st addr (hex) fix column disable (119th column is reserved for fixed stuff, 10 gbits/s mode only) dw_rx_ctl_v2_s0 (rw) dw_rx_no_fs 1 02500
112 112 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 18 elastic store (receive direction) 18.1 functional description of elastic store receive direction the receive elastic store (es) buffers gapped 83 mhz data and outputs 78 mhz data to absorb clock gapping of the fec/dw overheads and fec check bytes. data arrives to the receive es grouped as 32 bits in each slice. each group of 32 bits is written into the associated es location (128 locations x 32 bits) by 237/238 clock cycles (payload region of the fec/dw frame) out of 255 clock cycles (whole fec/dw frame) in the 83 mhz clock. data is read from the es by a 78 mhz clock. the relationship between read and write addresses is controlled in order to minimize signal delay and to guarantee data integrity at the same time. in the initial state, or after over/underflow, the write address is automatically reset to the predefined position (32 locations ahead of the read address), when the first sync pulse is received. in 10 gbits/s mode, all four elastic stores should work in synchronization. in some applications, the receive es is disabled and data is bypassed. in this case, the overflow/underflow alarm is not declared. by software control, the elastic store is forced to restart. table 85. elastic store (rx) register summary function register name (first occurrence) register bits qty. 1st addr (hex) rx es overflowing interrupt alarm es_alarm_s0 (w1c) es_rx_overflw_a 4 0201c rx es underflowing interrupt alarm es_alarm_s0 (w1c) es_rx_undrflw_a 4 0201c rx es overflowing interrupt alarm mask es_mask_s0 (r/w) es_rx_overflw_m 4 02058 rx es underflowing interrupt alarm mask es_mask_s0 (r/w) es_rx_undrflw_m 4 02058 rx es forced restart es_ctl_s0 (r/w) es_rx_restart 4 02130
agere systems inc. 113 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 19 sonet fec (bch weak/in band) supermacro 19.1 sonfec (bch weak/in band) introduction the following sections provide the functional description of the sonet weak fec supermacro core: in-band. the functional description includes requirements that must be met, as derived from various specifications. the weak fec supermacro core consists of the following: ? sonet sts-192/quad sts-48 bch macro core ? sonet sts-192/quad sts-48 framer ? sonet sts-192/quad sts-48 b1 monitoring ? sonet sts-192/quad sts-48 descrambler ? sonet sts-192/quad sts-48 alignment fifo (transmit only) ? sonet sts-192/quad sts-48 transpose demultiplexer ? sonet sts-192/quad sts-48 b2 monitoring ? sonet overhead/prbs payload insert processing ? sonet overhead/prbs payload monitor processing ? sonet sts-192/quad sts-48 b2 computing ? sonet sts-192/quad sts-48 transpose multiplexer ? sonet sts-192/quad sts-48 scrambler ? sonet sts-192/quad sts-48 b1 computing 19.2 functional description of sonet fec (bch weak/in band) supermacro the sonet fec (sonfec) supermacro incorporates all the sonet-related functions of the tfec0410g device. it performs the bch encoding of the incoming sts data in the transmit direction and bch decoding in the receive direction. in both directions, all the blocks that modify/monitor the data can be disabled. in the transmit direction, the incoming data is framed, optionally descrambled, and monitored for b1 bip errors. if loss of frame, loss of signal, or rdi/ais is detected, then the ais frames are generated and all the functions are disabled (including bch encoding). if no ais conditions exist, or no ais data is received, then the data is passed on to the overhead processing macro. the overhead processor inserts the provisioned overhead bytes (software, toac, default, or data as received). the complete sonet frame is then bch encoded and optionally scrambled before being sent out from this macro. in the receive direction, the incoming data is framed, optionally descrambled, and monitored for b1 bip errors. if loss of frame, loss of signal, or rdi/ais is detected, then ais frames are generated and all the functions are dis- abled (including bch decoding). if no ais conditions exist, or no ais data is received, then the data is error cor- rected by the bch decoder (if within its error correction capability) and then is passed on to the overhead processing macro. the overhead processor drops the overhead bytes on the toac channel and performs over- head byte analysis on individual bytes, if enabled. the complete sonet frame is then optionally scrambled before being sent out from this macro. in the receive direction, software can monitor the error correction performance through the bip error counts provided both before and after bch decoding. the b1 or b2 bip errors can be moni- tored before bch decoding for sd/sf detection. the b2 errors can be monitored before or after bch decoding for sd/sf detection. the sonet supermacro also supports two loopback modes: one on the line side and the other on the system side. individual disable controls for all the blocks allow operational flexibility within the device. as an example, in loop- back mode, one of the framers (of the two in the loop) can be disabled as the other one performs the framing. this avoids redundancy of alarm signals as well as reduces the delay in framing. since individual macros are indepen- dently controlled by software, care must be taken to program the mode (10 gbits/s mode/2.5 gbits/s mode) of each block. in virtual 10 gbits/s mode (in the transmit direction only), the incoming four 2.5 gbits/s mode sts-48 signals are frame aligned at the alignment fifo and then multiplexed to form one single 10 gbits/s mode sts-192 signal. the structure of sonet weak fec supermacro is shown in figure 48 on page 114.
114 114 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 19 sonet fec (bch weak/in band) supermacro (continued) 19.2 functional description of sonet fec (bch weak/in band) supermacro (continued) figure 48. sonet weak fec supermacro functional block diagram los/framer oh_payload processor j0, f1, aps, fsi(bch3), k2 rdi-l/ais-l, s1, rei-internal insert prbs payload insertion fmr_ohp_lof fmr_ohp_sef frm_sync/data data_i[128] sys_clk[3:0] sys_rst[3:0] descrambler b2 monitor t-demux b1 monitor b1 compute t-mux scrambler frm_sync/data frm_sync/data frm_sync/data mpu_cntrl los/framer fmr_ohp_lof fmr_ohp_sef frm_sync/data data_o[128] mpu_clk frm_sync/data frm_sync/data frm_sync/data b1 monitor descrambler t-demux b2 monitor b2 compute t-mux b1 compute scrambler data_o[128] data_i[128] sys_clk[3:0] sys_rst[3:0] mpu_cntrl mpu_clk oh_payload processor j0, f1, aps, fsi(bch3), k2 rdi-l/ais-l, s1, rei-internal insert prbs payload monitoring rx_toac_i/o tx_toac_i/o b2 compute tline2rline rsys2tsys rei/rdi_cntrl bch decode b2 monitor ais detection sonet supermacro transmit sonet supermacro receive ber sf/sd ber sf/sd ber sf/sd ber sf/sd detection & rdi/ais detection align fifo b1 insert b1 insert in mux out mux in mux bch encoder out mux reporting
agere systems inc. 115 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 19 sonet fec (bch weak/in band) supermacro (continued) 19.3 sonfec ais/rdi generation 19.3.1 sonfec (bch weak/in band) overview in sonfec, both transmit and receive overhead processors can generate ais. if loss of clock or loss of signal is detected, ais is generated and software cannot disable the ais generation (no internal frame generation). once the ais condition is cleared, a subsequent one or two frames may be corrupt (bips). 19.3.2 transmit ais the sonfec supermacro generates ais in the transmit direction under the following conditions: loss of clock. loss of signal. severely errored frame (sef) and sef ais generation is software enabled (tx_sef_ais_dis). loss of frame (lof) and lof ais generation is software enabled (tx_lof_ais_dis). line?ais frame is detected and line ais generation upon detection is software enabled (tx_line_ais_dis). line?ais frame generation is software enabled (tx_line_ais_ins). table 86. transmit ais control register summary register name register bits function ohp_tx_ais_rdi tx_sef_ais_dis ais generation due to sef condition disable. 0 = ais generated under sef. 1 = ais generation under sef disabled. tx_lof_ais_dis ais generation due to lof condition disable. 0 = ais generated under lof. 1 = ais generation under lof disabled. tx_line_ais_dis ais generation due to ais detect disable. 0 = ais generated under ais. 1 = ais generation under ais disabled. tx_line_ais_ins ais generation. 0 = ais generated. 1 = ais generation disabled.
116 116 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 19 sonet fec (bch weak/in band) supermacro (continued) 19.3 sonfec ais/rdi generation (continued) 19.3.3 receive ais the sonfec supermacro generates ais in the receive direction under the following conditions: loss of clock. loss of signal. severely errored frame (sef) and sef ais generation is software enabled (rx_sef_ais_dis). loss of frame (lof) and lof ais generation is software enabled (rx_lof_ais_dis). signal fail at post b2 monitoring and sf ais generation is software enabled (rx_sf_ais_dis). section trace?j0 mismatch and j0 mismatch ais generation is software enabled (rx_tim_l_ais_dis). line?ais frame is detected and line ais generation upon detection is software enabled (rx_line_ais_dis). line?ais frame generation is software enabled (rx_line_ais_ins). table 87. receive ais control register summary register name register bits function ohp_rx_ais_rdi rx_sef_ais_dis ais generation due to sef condition disable. 0 = ais generation due to sef enabled. 1 = ais generation due to sef disabled. rx_lof_ais_dis ais generation due to lof condition disable. 0 = ais generation due to lof enabled. 1 = ais generation due to lof disabled. rx_line_ais_dis ais generation due to ais detection disable. 0 = ais generation due to ais detect enabled. 1 = ais generation due to asi detect disabled. rx_tim_l_ais_dis ais generation due to j0 mismatch disable. 0 = ais generation due to j0 mismatch enabled. 1 = ais generation due to j0 mismatch disabled. rx_sf_ais_dis ais generation due to sf condition disable. 0 = ais generation due to sf condition enabled. 1 = ais generation due to sf condition disabled. rx_line_ais_ins ais generation. 0 = ais generation disabled. 1 = ais generated.
agere systems inc. 117 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 19 sonet fec (bch weak/in band) supermacro (continued) 19.3 sonfec ais/rdi generation (continued) 19.3.4 transmit rdi generation the sonfec supermacro generates rdi in the transmit direction whenever there is a hardware ais condition in the receive direction. once the receive direction detects any one of the rdi generation events, k2 bytes in the transmit direction are modified under all conditions (except in the case of software bypass). if no hardware rdi generation events are present, then the lower 3 bits of the software programmed k2 byte are inserted if software insert is enabled. once rdi is inserted, the duration can be software controlled for either 20 consecutive frames or the duration of the rdi event. both rdi and ais conditions are controlled by the same set of register bits. option- ally, software can be programmed to bypass the received k1/k2. table 88. transmit rdi insertion control register summary 19.4 sonfec interrupt structure the interrupt structure is comprised of different registers depending on the consolidation level. the structure depicts only that of the sonfec macro. individual interrupts sourced within the sonfec supermacro cause the corresponding bits to be set in the interrupt service register (alarm registers (w1c)). if the corresponding interrupt mask register bit is set (mask registers (r/w)), then these interrupts cause the sub- macro level interrupt bit to be set. these submacro level interrupts are grouped into two: overhead processor and bch. when the mask bits corresponding to these submacro interrupts are set, they cause an interrupt to be sourced from the sonfec supermacro. the interrupt summary is given the tfec0410g hardware register map document. register name register bits function ohp_tx_ais_rdi tx_20frm_rdi_dis rdi insertion disable. 0 = enable rdi insertion on 20 frames. 1 = disable rdi insertion on 20 frames. ohp_tx_maint tx_rdi_l_select rdi insertion from the programmed k2 byte enable. 0 = rdi insertion disabled. 1 = rdi insertion enabled. ohp_tx_k1k2 tx_k2_byte[3:0] if software enabled, then the last three bits of k2 are inserted in rdi.
118 118 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 20 bch macro 20.1 functional description of bch macro the bch (bose-chaudhuri-hocquenghem) macro performs in-band forward error correction (fec). the code used for in-band fec is a shortened, systematic binary bch (4359, 4320) code derived from a (8191, 8162) parent code which belongs to the family of systematic linear cyclic block codes. the code block consists of 4320 informa- tion bits and 39 check bits. in order to enhance the immunity of the transmission system to the burst errors, eight code blocks are bit-interleaved. figure 49. 8-way bit interleaved bch (4359, 4320) frame the 39 check bits are the remainder after polynomial division of the information polynomial by generating polyno- mial g(x) = g1(x) g3(x) g5(x) where g1(x) = x 13 +x 4 +x 3 +x+1, g3(x)=x 13 +x 10 +x 9 +x 7 +x 5 +x 4 +1, and g5(x) = x 13 +x 11 +x 8 +x 7 +x 4 + x + 1. sufficient check bits are generated to support triple error correction. the 8-way bit interleaving in conjunction with bch-3 provides 24-bit burst error correction capability per frame. one row of an stm-16 (sts-48), which is 4320 bytes, forms the information of the bch frame (i.e., the bch macro encodes and decodes the stm-16 (sts-48) on a row-by-row basis). the code block definition for an stm-64 (sts-196) is identical to that for an stm-16 (sts-48). however, there are four block groups, i.e., 32 code blocks. conceptually, the fec function falls below the multiplexing section (ms) layer and provides a correction service to the ms layer, and uses overhead bytes from the msoh (multiplexing section overhead) and rsoh (regenerator section overhead) as shown in figure 50 on page 119. although check bytes are transported in information byte positions, they are not included in information. from this, all rsoh bytes (including undefined rsoh bytes) and all fec check bytes are not included in the coding of the fec and are replaced with zeros. note that the q1 bytes (fsi?fec status indication bytes) are covered by the fec, and are therefore included in the coding of the fec. 39 bits (check) 4359 bits (code block) 4320 bits (information) 8 code blocks lsb msb 39 bytes (check) 4359 bytes (8-bit interleaved code blocks) 4320 bytes (information)
agere systems inc. 119 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 20 bch macro (continued) 20.1 functional description of bch macro (continued) figure 50. fec check byte allocation in stm-16 (sts-48) 9 rows 4320 columns (bytes) 144 columns 16 columns 9 rows group 1 fec 1 row = 2, group = 1 group 9 group 2 row = 2, group = 4 row = 2, group = 6 fec 2 row = 3, group = 1 row = 3, group = 4 row = 3, group = 6 fec 3 row = 3, group = 7 row = 3, group = 8 row = 3, group = 9 fec 4 row = 5, group = 4 row = 5, group = 5 row = 5, group = 6 fec 5 row = 5, group = 7 row = 5, group = 8 row = 5, group = 9 fec 6 row = 6, group = 7 row = 6, group = 8 row = 6, group = 9 fec 7 row = 7, group = 7 row = 7, group = 8 row = 7, group = 9 fec 8 row = 8, group = 7 row = 8, group = 8 row = 8, group = 9 fec 9 row = 9, group = 1 row = 9, group = 2 row = 9, group = 2 q1 byte 8 bits 1 bit 8-bit interleaved 8-bit interleaved check data #0 check data #12 1 2 3 4 5 6 7 8 9 101112131415 16 byte no.
120 120 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 20 bch macro (continued) 20.1 functional description of bch macro (continued) in figure 44 on page 91, each set of fec bytes represents a set of fec check bits. the number indicates the row of the payload to which each set of fec check bytes pertains. the q1 byte is an fec status indicator (fsi). this is used at the fec decoding point to determine whether fec information is present for error correction to take place. table 89 and table 90 give the exact check byte locations for stm-16 and stm-64 signals. table 89. location of fec check bits for stm-64 (sts-192) the numbers in the table represent row number, group number, and byte number, respectively. fec row # 1 1. see figure 50, fec check byte allocation in stm-16 (sts-48), on page 119 for details on fec rows. check bits set #1 (#38 ~ #26) check bits set #2 (#25 ~ #13) check bits set #3 (#12 ~ #0) q1 byte 1 2, 1, 4 ~ 2, 1, 16 2, 4, 4 ~ 2, 4, 16 2, 6, 4 ~ 2, 6, 16 ? 2, 1, 20 ~ 2, 1, 32 2, 4, 20 ~ 2, 4, 32 2, 6, 20 ~ 2, 6, 32 2, 1, 36 ~ 2, 1, 48 2, 4, 36 ~ 2, 4, 48 2, 6, 36 ~ 2, 6, 48 2, 1, 52 ~ 2, 1, 64 2, 4, 52 ~ 2, 4, 64 2, 6, 52 ~ 2, 6, 64 2 3, 1, 4 ~ 3, 1, 16 3, 4, 4 ~ 3, 4, 16 3, 6, 4 ~ 3, 6, 16 3, 1, 20 ~ 3, 1, 32 3, 4, 20 ~ 3, 4, 32 3, 6, 20 ~ 3, 6, 32 3, 1, 36 ~ 3, 1, 48 3, 4, 36 ~ 3, 4, 48 3, 6, 36 ~ 3, 6, 48 3, 1, 52 ~ 3, 1, 64 3, 4, 52 ~ 3, 4, 64 3, 6, 52 ~ 3, 6, 64 3 3, 7, 4 ~ 3, 7, 16 3, 8, 4 ~ 3, 8, 16 3, 9, 4 ~ 3, 9, 16 3, 9, 3 (fsi) 3, 7, 20 ~ 3, 7, 32 3, 8, 20 ~ 3, 8, 32 3, 9, 20 ~ 3, 9, 32 3, 9, 19 (00h) 3, 7, 36 ~ 3, 7, 48 3, 8, 36 ~ 3, 8, 48 3, 9, 36 ~ 3, 9, 48 3, 9, 35 (00h) 3, 7, 52 ~ 3, 7, 64 3, 8, 52 ~ 3, 8, 64 3, 9, 52 ~ 3, 9, 64 3, 9, 51 (00h) 4 5, 4, 4 ~ 5, 4, 16 5, 5, 4 ~ 5, 5, 16 5, 6, 4 ~ 5, 6, 16 ? 5, 4, 20 ~ 5, 4, 32 5, 5, 20 ~ 5, 5, 32 5, 6, 20 ~ 5, 6, 32 5, 4, 36 ~ 5, 4, 48 5, 5, 36 ~ 5, 5, 48 5, 6, 36 ~ 5, 6, 48 5, 4, 52 ~ 5, 4, 64 5, 5, 52 ~ 5, 5, 64 5, 6, 52 ~ 5, 6, 64 5 5, 7, 4 ~ 5, 7, 16 5, 8, 4 ~ 5, 8, 16 5, 9, 4 ~ 5, 9, 16 5, 7, 20 ~ 5, 7, 32 5, 8, 20 ~ 5, 8, 32 5, 9, 20 ~ 5, 9, 32 5, 7, 36 ~ 5, 7, 48 5, 8, 36 ~ 5, 8, 48 5, 9, 36 ~ 5, 9, 48 5, 7, 52 ~ 5, 7, 64 5, 8, 52 ~ 5, 8, 64 5, 9, 52 ~ 5, 9, 64 6 6, 7, 4 ~ 6, 7, 16 6, 8, 4 ~ 6, 8, 16 6, 9, 4 ~ 6, 9, 16 ? 6, 7, 20 ~ 6, 7, 32 6, 8, 20 ~ 6, 8, 32 6, 9, 20 ~ 6, 9, 32 6, 7, 36 ~ 6, 7, 48 6, 8, 36 ~ 6, 8, 48 6, 9, 36 ~ 6, 9, 48 6, 7, 52 ~ 6, 7, 64 6, 8, 52 ~ 6, 8, 64 6, 9, 52 ~ 6, 9, 64 7 7, 7, 4 ~ 7, 7, 16 7, 8, 4 ~ 7, 8, 16 7, 9, 4 ~ 7, 9, 16 7, 7, 20 ~ 7, 7, 32 7, 8, 20 ~ 7, 8, 32 7, 9, 20 ~ 7, 9, 32 7, 7, 36 ~ 7, 7, 48 7, 8, 36 ~ 7, 8, 48 7, 9, 36 ~ 7, 9, 48 7, 7, 52 ~ 7, 7, 64 7, 8, 52 ~ 7, 8, 64 7, 9, 52 ~ 7, 9, 64 8 8, 7, 4 ~ 8, 7, 16 8, 8, 4 ~ 8, 8, 16 8, 9, 4 ~ 8, 9, 16 8, 7, 20 ~ 8, 7, 32 8, 8, 20 ~ 8, 8, 32 8, 9, 20 ~ 8, 9, 32 8, 7, 36 ~ 8, 7, 48 8, 8, 36 ~ 8, 8, 48 8, 9, 36 ~ 8, 9, 48 8, 7, 52 ~ 8, 7, 64 8, 8, 52 ~ 8, 8, 64 8, 9, 52 ~ 8, 9, 64 9 9, 1, 4 ~ 9, 1, 16 9, 2, 4 ~ 9, 2, 16 9, 3, 4 ~ 9, 3, 16 9, 1, 20 ~ 9, 1, 32 9, 2, 20 ~ 9, 2, 32 9, 3, 20 ~ 9, 3, 32 9, 1, 36 ~ 9, 1, 48 9, 2, 36 ~ 9, 2, 48 9, 3, 36 ~ 9, 3, 48 9, 1, 52 ~ 9, 1, 64 9, 2, 52 ~ 9, 2, 64 9, 3, 52 ~ 9, 3, 64
agere systems inc. 121 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 20 bch macro (continued) 20.1 functional description of bch macro (continued) table 90. location of fec check bits for stm-16 (sts-48) 20.1.1 bch encoder the bch encoder generates and inserts check bits of stm-16/stm-64 (sts-48/sts-192) signals. data arrives to the bch encoder grouped as four slices of 32 bits. because the code block definition for an stm-64 (sts-192) is identical to that for an stm-16 (sts-48), and the transpose demultiplexer (tdmx) reorders the data so that the stm-64 (sts-192) is divided into its four constituent sts-48 data streams, each slice can operate independently even in stm-64 (sts-192) mode. the only difference between stm-16 (sts-48) mode and stm-64 (sts-192) is q1 byte insertion, which is explained in the next section (section 20.1.1.1). 20.1.1.1 fsi bit insert the fec encoder is required to generate the fec status indication (fsi) bits to enable downstream decoders. this is to prevent downstream decoders from causing miscorrection when fec encoding is not present. the q1 byte is located in row 3, as shown in figure 49 on page 118. the fsi carrying byte is located in the first q1 byte, i.e., the q1 byte of the first block group (which contains fsi and q1 bytes in the remaining block groups) is unassigned and the transmitted default value is 00h in stm-64 (sts-192) mode. the fsi bits are the bits (7 and 8) of the fsi byte, as shown in figure 51. the remaining bits in the fsi byte are reserved, but are covered by the fec. the transmitted default value for these remaining 6 bits is zero. figure 51. fec status indication byte (fsi) the value of the fsi bits is encoded according to encoder states, and there are three operational encoder states: fec-on, fec-off with encoder delay, and fec-off without encoder delay. the encoder operational state is controlled by software. when the encoder is in the fec-on state, fsi = 01 is transmitted. when the encoder is in the fec-off with encoder delay state, all q1 bytes are set to 000. when the encoder is in the fec-off without encoder delay state, they are bypassed. note: 10 or 11 is not a valid encoder transmission value. fec row # 1 1. see figure 50, fec check byte allocation in stm-16 (sts-48), on page 119 for details on fec rows. check bits set #1 (#38 ~ #26) check bits set #2 (#25 ~ #13) check bits set #3 (#12 ~ #0) q1 byte 1 2, 1, 4 ~ 2, 1, 16 2, 4, 4 ~ 2, 4, 16 2, 6, 4 ~ 2, 6, 16 ? 2 3, 1, 4 ~ 3, 1, 16 3, 4, 4 ~ 3, 4, 16 3, 6, 4 ~ 3, 6, 16 3 3, 7, 4 ~ 3, 7, 16 3, 8, 4 ~ 3, 8, 16 3, 9, 4 ~ 3, 9, 16 3, 9, 3 4 5, 4, 4 ~ 5, 4, 16 5, 5, 4 ~ 5, 5, 16 5, 6, 4 ~ 5, 6, 16 ? 5 5, 7, 4 ~ 5, 7, 16 5, 8, 4 ~ 5, 8, 16 5, 9, 4 ~ 5, 9, 16 6 6, 7, 4 ~ 6, 7, 16 6, 8, 4 ~ 6, 8, 16 6, 9, 4 ~ 6, 9, 16 7 7, 7, 4 ~ 7, 7, 16 7, 8, 4 ~ 7, 8, 16 7, 9, 4 ~ 7, 9, 16 8 8, 7, 4 ~ 8, 7, 16 8, 8, 4 ~ 8, 8, 16 8, 9, 4 ~ 8, 9, 16 9 9, 1, 4 ~ 9, 1, 16 9, 2, 4 ~ 9, 2, 16 9, 3, 4 ~ 9, 3, 16 reserved fsi 1 2 3 4 5 6 7 8
122 122 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 20 bch macro (continued) 20.1 functional description of bch macro (continued) table 91. bch macro register summary note: when configuring the bch encoder in oc-192 mode, ensure that all slices are enabled. to ensure all slices are active befor e the fsi byte is generated, write 01147 last. 20.1.1.2 fec payload generate all rsoh bytes (including undefined rsoh bytes) of incoming stm-16 (sts-48) signals are not included in the encoding of the fec and are replaced with zeros before the check bit calculation. all q1 bytes are included in the fec block for correction before retransmission by correcting regenerators, and therefore are added to the incoming stm-16 (sts-48) signal for the encoding of the fec. 20.1.1.3 check bit generate data arrives to the bch encoder grouped as four slices of 32 bits. the bch encoder generates check bits in 8-way bit interleaving mode. therefore, there are 4 bits of data which belong to the same code block at every clock cycle. each slice has eight independent check bit calculators. each calculator accepts 4 bits of information data which belong to same code block during 1080 clock cycles (i.e., accepts 4320 information bits). after 1080 times polyno- mial division of the information data, each calculator outputs 39 bits check data, which is a remainder of the polyno- mial division. since the in-band fec code blocks are designed to cover a single row of the stm-16 (sts-48), the starting of polynomial division is the same as starting each row of the stm-16 (sts-48). 20.1.1.4 check bit insert the check bits are inserted into designated locations as shown in figure 44 on page 91. the check bit data is available after polynomial division of the associated information data, but fec-3, fec-5, fec-6, fec-7, fec-8, and fec-9 are located in the middle of the rows to which the check bit data pertains. for this reason, information data is delayed before check bit inserting. as mentioned previously, there are three operational encoding states. the fec insert works in synchronization with the encoding state. when the encoder operates in the fec-off without encoder delay state, the information data is transmitted without delay. in order to permit synchronized decoder switching at the receiver, the fec insert is turned off (on) starting with the first row of the eighth frame after the fsi change. for flexible operation, check bits are inserted either msb first or lsb first. this is configured by software. table 92. bch fec insert register summary function register name (first occurrence) register bits qty. 1st addr (hex) bch encoder status control bch_prov_s0 (r/w) bch_enc_mode 4 01144 function register name (first occurrence) register bits qty. 1st addr (hex) bch fec insert control bch_prov_s0 (r/w) bch_enc_insert 4 01144
agere systems inc. 123 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 20 bch macro (continued) 20.1 functional description of bch macro (continued) 20.1.1.5 b2 compensate since the fec function uses overhead bytes from the msoh and consequently overwrites bytes currently covered by b2, the bch encoder compensates b2 appropriately to reflect the change in the fec msoh bytes; the fec check bits cover the b2 byte. the fec check bytes and fsi byte in the rsoh are not included in b2 compensation; only the fec check bytes in the msoh are included in b2 compensation. this ensures backward compatibility of b1 and b2 calculation for non- fec equipment. 20.1.1.6 error insert various types of errors can be inserted for bch code testing. the error insert inserts various types of errors for bch code testing. for each slice, an error insert block accepts 32 bits of data. there are a total of 4 slices instanti- ated to create the 128-bit wide data for 16-way and 64-way 10 gbits/s mode. a 32-bit mask register corresponds to the 32-bit wide data bus for the error insertion. when the mask bit is set to logic 1, the corresponding data bit is inverted. the number of skipping clock cycles can be programmed through the microprocessor. error bits combining with the number of skipping clock cycles can be repeated by using a con- trol bit bus. the first column of error can be chosen via the microprocessor. the stream of errors start when there is a 0 ? 1 transition on the error control bit. note: to ensure all errors are inserted within the valid range, the following equation can be used: (skip + 1) (repeat ? 1) + row 1080 + column < 9 1080 table 93. bch error insert register summary function register name (first occurrence) register bits qty. 1st addr (hex) mask for error insertion on the 32-bit data bus bch_txerr_maskl_s0/ bch_txerr_masku_s0 (r/w) bch_txerr_mask_l/ bch_txerr_mask_u 4 01148/ 0114c number of skipping clock cycles between the 32-bit error patterns (valid range is 0?1023) bch_txerr_skip_s0 (r/w) bch_txerr_skip 4 01158 number of repeating clock cycles between the 32-bit error patterns (valid range is 0 (no error)?255) bch_txerr_repeat_s0 (r/w) bch_txerr_repeat 4 01154 start row (valid range is 0?8) bch_txerr_rowcol_s0 (r/w) bch_txerr_row 4 01150 start column (valid range is 0?1079) bch_txerr_rowcol_s0 (r/w) bch_txerr_col 4 01150 error start control bit bch_txerr_start_s0 (r/w) bch_txerr_start 4 01158 error insert finish state bch_tx_state_s0 (ro) bch_txerr_finish 4 010e4 error insert finish alarm bch_tx_alarm_s0 (w1c) bch_txerr_finish_a 4 01020 error insert finish mask bch_tx_mask_s0 (r/w) bch_txerr_finish_m 4 0106c error insert finish persist bch_tx_persist_s0 (ro) bch_txerr_finish_p 4 010b4
124 124 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 20 bch macro (continued) 20.1 functional description of bch macro (continued) 20.1.2 bch decoder the bch decoder detects and corrects transmission errors of stm-16/stm-64 (sts-48/sts-192) signals. data arrives to the bch decoder grouped as four slices of 32 bits. because the code block definition for an stm-64 (sts-192) is identical to that of an stm-16 (sts-48), and the transpose demultiplexer (tdmx) reorders the data so that the stm-64 (sts-192) is divided into its four constituent sts-48 data streams, each slice can operate inde- pendently even in stm-64 (sts-192) mode. one difference between stm-16 (sts-48) mode and stm-64 (sts-192) is q1 byte interpretation, which will be explained in section 20.1.2.3 on page 125. when defects (loc/los/oof/lof/ms-ais) are found, the associated bch decoder is disabled. the diagram of the bch decoder, in each slice, is shown in figure 48 on page 114. 20.1.2.1 fec frame generate all rsoh bytes (including undefined rsoh bytes) of incoming stm-16 (sts-48) signals are not included in the decoding of the fec and are replaced with zeros before error detection. all q1 bytes are corrected before retrans- mission by correcting regenerators, and therefore are included in the decoding of the fec. for flexible operation, check bits are extracted in either msb first or lsb first. this is configured by software. table 94. bch frame generate register summary 20.1.2.2 error detect each slice has eight independent error detect blocks and each detect block consists of three subblocks: syndrome calculate, bma (berlekamp-massey algorithm), and chien (time-domain error location) search. uncorrectable errors are detected and reported to the bch stat as well as corrected bits, per slice. function register name (first occurrence) register bits qty. 1st addr (hex) bch fec extract control bch_rxprov_s0 (r/w) bch_dec_extract 4 01140
agere systems inc. 125 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 20 bch macro (continued) 20.1 functional description of bch macro (continued) 20.1.2.3 fsi bit interpret in hardware mode, the fec decoder is required to interpret the fec status indication (fsi) bits to enable correct- ing function. this is to prevent miscorrection when fec encoding is not present. the q1 byte locations and fsi bits information are the same as those of the encoder. when the bch decoder operates in stm-64 (sts-192) mode, the fsi carrying byte is located in the first q1 byte, and therefore, decoding states of the slices which have the second, third, and fourth q1 bytes follow that of the master slice, which has the first q1 byte. the decoding state transition according to the received fsi is as follows. the decoding state can be changed from fec-on to fec-off with encoder delay upon receipt of third consecutive non-01, and from fec-off with encoder delay to fec-on upon receipt of the ninth consecutive fsi value 01. table 95. bch fsi register summary 20.1.2.4 error correct the received data is delayed before being corrected, while transmission errors are detected. there are two ways of controlling decoding states. the first is by hardware (fsi controlled) and the second is by software. when the bch decoder is set to hardware mode, the correcting function will follow the fsi as mentioned above. the state transition between fec-on and fec-off is hitless. in software mode, there are the four following decoding states. two are the same as hardware mode, and moni- toring and shutdown modes are added: ?fec-on. ? fec-off with decoder delay. ? monitoring (error detect and count but not correct without decoder delay). ? shutdown (no error detect nor correct). in monitoring and shut-down modes, the received data is transmitted downstream without delay. table 96. bch decoding register summary 20.1.3 bch statistics (bch-stat) the bch-stat counts correctable errors that are detected and corrected in the bch decoder. the monitoring of the line ber before correction can be done through the knowledge of the exact number of corrected bits. the errors that remain uncorrected after forward error correction can be considered negligible in the computation of ber for low error rates. function register name (first occurrence) register bits qty. 1st addr (hex) bch correction status bch_rx_state_s0 (ro) bch_dec_fsi 4 010e0 bch correction status interrupt alarm bch_rx_alarm_s0 (w1c) bch_dec_fsi_a 4 0101c bch correction status interrupt mask bch_rx_mask_s0 (r/w) bch_dec_fsi_m 4 01068 bch correction status persistency bch_rx_persist_s0 (ro) bch_dec_fsi_p 4 010b0 function register name (first occurrence) register bits qty. 1st addr (hex) bch decoding mode select bch_rxprov_s0 (r/w) bch_dec_mode 4 01140
126 126 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 20 bch macro (continued) 20.1 functional description of bch macro (continued) 20.1.3.1 error count the corrected bits and the uncorrectable blocks are accumulated per slice in 16-bit saturating counters based on either bit or block errors. in bit mode, each corrected error (or uncorrectable block) causes the counter to incre- ment. if block error is selected, each bch frame which has a corrected error (or uncorrectable block) causes the counter to increment by one. the counter will stop at the maximum value, will not roll over, and is cleared by the pmrst signal. table 97. bch error count register summary 20.1.3.2 ber monitor the corrected errors are used to detect sf and sd conditions. the ber threshold for each defect is separately provisionable for each slice over a range of 1 10 ?n values, where n = 3 to 9. the ber algorithm is the same as that of the rs decoder (refer to section 16.1.2, ber monitor, on page 89 for a detailed description). table 98. ber threshold time and error limits for line sd and sf detection the sd/sf ber control bits select the bit error rate for a particular slice. these control bits then select the detec- tion time, detect error limit, and clear error limit for each slice. the detect error limit and the clear error limit regis- ters contain 16-bit values, while the detection time registers use the lower 15 bits for a value and the upper bit for a time unit specifier. for the detection time register, the value contained in the lower 15 bits is either specified in 0.125 ms units (upper bit = 0) or in 0.128 s units (upper bit = 1). note: the receive sync pulse is used as the timing reference. function register name (first occurrence) register bits qty. 1st addr (hex) bch error count control bch_err_prov_s0 (r/w) bch_err_bitblk 4 0115c bch rx corrected bit counter bch_err_bitcnt_l_s0/ bch_err_bitcnt_u_s0 (ro) bch_err_bitcnt_l/ bch_err_bitcnt_u 4 01165/ 01164 bch rx uncorrectable block counter bch_err_blkcnt_l_s0/ bch_err_blkcnt_u_s0 (ro) bch_unc_blkcnt_l/ bch_unc_blkcnt_u 40116e/ 0116d ber threshold detection time detect error limit clear error limit sts-48/ stm-16 sts-192/ stm-64 sts-48/ stm-16 sts-192/ stm-64 sts-48/ stm-16 sts-192/ stm-64 1 10 ?3 1.0 ms 0.25 ms 992 992 ? ? 1 10 ?4 1.0 ms 0.25 ms 248 248 496 496 1 10 ?5 4.0 ms 1.0 ms 99 99 495 495 1 10 ?6 32.0 ms 8.0 ms 79 79 395 395 1 10 ?7 128.0 ms 32.0 ms 63 63 315 315 1 10 ?8 1 s 250 ms 50 50 250 250 1 10 ?9 8.2 s 2.1 s 40 40 200 200 1 10 ?10 65.6 s 16.4 s ? ? 160 160
agere systems inc. 127 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 20 bch macro (continued) 20.1 functional description of bch macro (continued) table 99. bch ber monitor register summary function register name (first occurrence) register bits qty. 1st addr (hex) bch sd threshold select bch_err_prov_s0 (r/w) bch_rx_ber_sd 4 0115c bch sf threshold select bch_err_prov_s0 (r/w) bch_rx_ber_sf 4 0115c bch sd detect bch_state_s0 (ro) bch_rx_ber_sd_det 4 010e0 bch sf detect bch_state_s0 (ro) bch_rx_ber_sf_det 4 010e0 bch sd detect alarm bch_alarm_s0 (w1c) bch_rx_ber_sd_det_a 4 0101c bch sf detect alarm bch_alarm_s0 (w1c) bch_rx_ber_sf_det_a 4 0101c bch sd detect mask bch_mask_s0 (r/w) bch_rx_ber_sd_det_m 4 01168 bch sf detect mask bch_mask_s0 (r/w) bch_rx_ber_sf_det_m 4 01168 bch sd detect persistency bch_persist_s0 (ro) bch_rx_ber_sd_det_p 4 010b0 bch sf detect persistency bch_persist_s0 (ro) bch_rx_ber_sf_det_p 4 010b0 bch ber report bch_err_rpt_s0 (ro) bch_ber_report 4 01160 bch ber-3 detection time bch_berdt3 (r/w) bch_ber_dt_unit_3/ bch_ber_dt_val_3 1 01190 bch ber-4 detection time bch_berdt4 (r/w) bch_ber_dt_unit_4/ bch_ber_dt_val_4 1 01191 bch ber-5 detection time bch_berdt5 (r/w) bch_ber_dt_unit_5/ bch_ber_dt_val_5 1 01192 bch ber-6 detection time bch_berdt6 (r/w) bch_ber_dt_unit_6/ bch_ber_dt_val_6 1 01193 bch ber-7 detection time bch_berdt7 (r/w) bch_ber_dt_unit_7/ bch_ber_dt_val_7 1 01194 bch ber-8 detection time bch_berdt8 (r/w) bch_ber_dt_unit_8/ bch_ber_dt_val_8 1 01195 bch ber-9 detection time bch_berdt9 (r/w) bch_ber_dt_unit_9/ bch_ber_dt_val_9 1 01196 bch ber-10 detection time bch_berdt10 (r/w) bch_ber_dt_unit_10/ bch_ber_dt_val_10 1 01197 bch ber-3 detect error limit bch_berset3 (r/w) bch_ber_set_limit_3 1 011c0 bch ber-4 detect error limit bch_berset4 (r/w) bch_ber_set_limit_4 1 011c1 bch ber-5 detect error limit bch_berset5 (r/w) bch_ber_set_limit_5 1 011c2 bch ber-6 detect error limit bch_berset6 (r/w) bch_ber_set_limit_6 1 011c3 bch ber-7 detect error limit bch_berset7 (r/w) bch_ber_set_limit_7 1 011c4 bch ber-8 detect error limit bch_berset8 (r/w) bch_ber_set_limit_8 1 011c5 bch ber-9 detect error limit bch_berset9 (r/w) bch_ber_set_limit_9 1 011c6 bch ber-4 clear error limit bch_berclr4 (r/w) bch_ber_clr_limit_4 1 011f0 bch ber-5 clear error limit bch_berclr5 (r/w) bch_ber_clr_limit_5 1 011f1 bch ber-6 clear error limit bch_berclr6 (r/w) bch_ber_clr_limit_6 1 011f2 bch ber-7 clear error limit bch_berclr7 (r/w) bch_ber_clr_limit_7 1 011f3 bch ber-8 clear error limit bch_berclr8 (r/w) bch_ber_clr_limit_8 1 011f4 bch ber-9 clear error limit bch_berclr9 (r/w) bch_ber_clr_limit_9 1 011f5 bch ber-10 clear error limit bch_berclr10 (r/w) bch_ber_clr_limit_10 1 011f6
128 128 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 21 sonfec input mux and output mux 21.1 functional description of sonec input mux and output mux the sonfec input mux and output mux transfer data across the slices depending upon their mode of operation. in 2.5 gbits/s mode, they bypass the data received. in 10 gbits/s mode, they transfer data across slices to/from four aggregate 32 bits of data on each of the slice clocks. the input mux also performs the loopback functionality in sonfec. 22 loss-of-signal (los) detector and framer 22.1 functional description of los detector and framer the los detector monitors the data for loss of signal. the framer macro generates the frame sync and loss-of- frame outputs. these functions can be optionally disabled, allowing data to pass through unchanged. the framer also generates an 8 khz reference output. 22.1.1 loss-of-signal (los) detector the data is monitored by the los detector macro for loss of signal (los). in sts-192 mode, there is a single los detector. in sts-48 mode, there is a separate los detector on each sts-48 input. on powerup, an los defect is declared if all zeros data is received continuously for a programmable time threshold. this time threshold is provi- sional through the loss-of-signal (los) threshold register for each channel, and can be set to any value from 0 s (i.e., los detection disabled) to 105 s, with a resolution of 102.88 ns (64 times the period of the 622.08 mhz clock). the los defect is subsequently cleared when two successive valid framing patterns are received with no period of all zeros exceeding the time threshold. detection of an los defect is indicated by a latched alarm status bit, a per- sistency bit, and a 1 s pm bit being set in the corresponding lte receive channel registers. in addition, los causes alarm indication signal (ais) generation by the overhead processor block in all sts-48 or sts-192 affected. both the transmit and receive los detectors are identical. 22.1.2 framer (a1 and a2) in sts-192 mode, framing is performed on a single channel. in sts-48 mode, framing is performed on four inde- pendent channels. the framer also supports enhanced framing, where every other a1 byte and a2 byte is inverted to better maintain dc balance on the optical line. a1a1 a1a1 ...a1a1 = f609f609 . . . f609. a2a2 a2a2 ...a2a2 = 28d728d7 . . . 28d7. the sts framing bytes are present in all sts-1 time slots of the sts-48 or sts-192. when normal framing is selected, the a1 bytes are set to 0xf6, while the a2 bytes are set to 0x28. if enhanced framing is selected, using the framing mode control bit, the a1 and a2 bytes contain normal framing in odd sts-1 time slots and the inverse value in even sts-1 time slots. the framer outputs frame-aligned data and the 8 khz reference (free-running) sig- nal. the sts-192 framer is described in the following sections. the sts-48 framer is similar.
agere systems inc. 129 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 22 loss-of-signal (los) detector and framer (continued) 22.1 functional description of los detector and framer (continued) 22.1.2.1 framer fsm the framer finite state machine (fsm) is responsible for determining the severely errored framing (sef) and loss- of-framing (lof) sonet framing alarms for each channel. the framer fsm is shown in figure 52. the fsm comes out of reset in the sef state with the sef and lof alarms active. the framing pattern used is the 16-bit word consisting of the last a1 byte and the first a2 byte. the first occurrence of the framing pattern transfers the fsm to the frame confirm state. frame timing is also synchronized. another framing pattern that matches coin- cident with the expected frame timing transfers the state to in-frame (i.e., it takes two consecutive valid framing pat- terns to frame to an incoming signal). outside the sef and frame confirm states, the sef alarm output is inactive. as shown in the fsm, when in-frame, four consecutive framing errors are required to be transferred back to the sef state. the lof alarm is asserted if sef persists for 24 frames (3 ms). the lof alarm is terminated eight frames (1 ms) after the sef alarm is terminated (i.e., eight frames after the fsm enters the in-frame state), provided the sef state is not reentered (as per sonet objectives). the framing pattern is a subset of the a1a2 sts-n pattern. this design uses the 16-bit a1a2 boundary as the framing pattern which evaluates to an average sef defect occurrence time of 31.79 min., assuming a poisson bit error rate (ber) of 10 ?3 . this is greater than the minimum average sonet requirement of 6 min. the sef alarm is reported by a latched register bit in the lte receive nonservice-affecting alarm register for the respective channel. the lof alarm is reported by a latched register bit in the lte receive service-affecting alarm register for the respective channel. in addition, a persistency bit for lof exists in the lte receive service-affecting persistency register. detection of lof and sef defects are also indicated by the lte receive last-second pm reg- ister. detected lof defect detection causes ais to be inserted in all affected sts-48 or sts-192. this ais insertion is disabled by default after reset and can be enabled using the lof ais disable control register bit for each channel, or replaced by insertion upon sef detection using the sef ais disable control bit. another control bit is the enhanced framing mode bit. these control bits are part of the lte provisioning register for the respective channel. figure 52. framer fsm framing pattern reset sef frame confirmed framing pattern found framing pattern not comfirmed four consecutive framing errors confirm in frame
130 130 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 22 loss-of-signal (los) detector and framer (continued) 22.1 functional description of los detector and framer (continued) table 100. framer register summary table 101. los detector register summary function register name (first occurrence) register bits qty. 1st addr (hex) framer disable control sonfec_rx_bypass_s0 (r/w) ohp_rx_frm_dis 4 01115 framer mode control sonfec_rx_mode (r/w) rx_frm_mode 1 01110 enhanced framing enable ohp_rx_prov_s0 (r/w) rx_enh_frmg_enb 4 01310 ais insertion on sef ohp_rx_prov_s0 (r/w) rx_sef_ais_dis 4 01314 ais insertion on lof ohp_rx_prov_s0 (r/w) rx_lof_ais_dis 4 01314 lof state ohp_rx_sa_state_s0 (ro) rx_lof 4 010e8 sef state ohp_rx_nsa_0_state_s0 (ro) rx_sef 4 010ec lof alarm ohp_rx_sa_alarm_s0 (w1c) rx_lof_a 4 01024 sef alarm ohp_rx_nsa_0_alarm_s0 (w1c) rx_sef_a 4 0102c lof alarm mask ohp_rx_sa_mask_s0 (r/w) rx_lof_m 4 01070 sef alarm mask ohp_rx_nsa_0_mask_s0 (r/w) rx_sef_m 4 01078 lof persistency ohp_rx_sa_persist_s0 (ro) rx_lof_p 4 010b8 sef persistency ohp_rx_nsa_0_persist_s0 (ro) rx_sef_p 4 010bc lof pm ohp_rx_pm_s0 (ro) rx_lof_pm 4 0132c sef pm ohp_rx_pm_s0 (ro) rx_sef_pm 4 0132c function register name (first occurrence) register bits qty. 1st addr (hex) los detection mode control sonfec_rx_mode (r/w) rx_los_mode 1 01110 los detect time threshold ohp_rx_los_s0 (r/w) rx_los_threshold 4 01324 los state ohp_rx_sa_state_s0 (ro) rx_los 4 010e8 los alarm ohp_rx_sa_alarm_s0 (w1c) rx_los_a 4 01024 los alarm mask ohp_rx_sa_mask_s0 (r/w) rx_los_m 4 01070 los persistency ohp_rx_sa_persist_s0 (ro) rx_los_p 4 010b8 los pm ohp_rx_pm_s0 (ro) rx_los_pm 4 0132c
agere systems inc. 131 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 23 transmit alignment fifo 23.1 functional description of transmit alignment fifo the alignment fifo block will align four independent 2.5 gbits/s data channels into one 10 gbits/s data channel. elastic buffers (fifos) are used to align each incoming 2.5 gbits/s stream (slice 1, slice 2, and slice 3) to the mas- ter 77.76 mhz clock (slice 0). these fifos will absorb delay variations of up to 1000 ns between the first and the last incoming 2.5 gbits/s streams, given that the four streams are byte-synchronous (on the byte boundary). each input 2.5 gbits/s data channel may be inhibited from contributing to the overall alignment by setting the corre- sponding inhibit bit (algn_inh) high. when one particular channel is inhibited from being aligned with the rest, the frame pulse for that channel is aligned with the aligned frame pulses of the rest of the channels and the data is brought out as all ones. the fifo depths can be monitored to give an indication of the individual operating depths (write address?read address). in addition, an overflow bit, when set using fifo_min and fifo_max values, will indicate the fifo full- ness or emptiness for each channel. the global resync signal will align all the channels when there is a 0 to 1 transition on the glbl_resync input. there is an alarm bit which will indicate if the alignment is not correct for a particular channel. if the alarm bit for a particular channel is high (indicating that the channel did not get aligned), the frame pulse for that channel is aligned with the pseudoframe pulse and the data is all ones. the pseudoframe pulse is the output of a free-running counter when there is no alignment performed. after alignment, the pseudoframe pulse occurs at the same position as the frame pulses from aligned channels. note: the global resync signal must be asserted if the original delay increases between the streams. the bypass input signal will cause the alignment to be bypassed and the data streams will be brought out as if it came in on time. (the input bits mpu_sonfec_tx_10g_2g5, v10g_mode_n, and bypass should all be set to zeros in order for the alignment to take place. this block also supports short-frame mode.) to use the alignment fifo on tx side, all four groups of four bits (16 bits total) must be frequency and phase aligned on arrival. internally, only the slice 0 clock is used (this is related to virtual 10 gbits/s mode). in this instance, it is important to understand that the alignment fifo in the sonfec block is used to frame align the four streams. the fifo alarm bit indicates if a stream is not correctly aligned with the other frames. a global resync is needed for alignment if the original delay increases between the inputs. while the delay between the inputs is less than the original delay, the device absorbs the delay variation automatically and no global resync is needed.
132 132 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 24 b1 monitoring 24.1 functional description of b1 monitoring the section bip-8 byte is located in the first sts-1 of the sts-48 or sts-192 only, and carries the even parity of the scrambled data in the previous sts-48 or sts-192 frame. in every frame, the received b1 value is extracted and compared to the calculated bip-8 for the previous frame. errors in the bip-8 code are tabulated in an internal 16-bit counter based on either bit or block errors, as provisioned for each channel through the b1 bip mode control bit. in bit mode (selected by default), each bip-8 bit in error causes the counter to increment. if block error is selected, each bip-8 code in error causes the counter to increment only once. regardless of which mode is selected, the value in the counter is transferred to the section coding violation (cv-s) register on the rising edge of the perfor- mance monitoring clock, at which point the counter is cleared. the counter will stop at the maximum value and will not roll over. table 102. b1 monitoring register summary 25 descrambler 25.1 functional description of the descrambler the data from the framer is optionally descrambled using the sonet/sdh standard generator polynomial: 1+x 6 +x 7 . the descrambling can be disabled through the descrm_dis bit in the lte receive channel provision- ing register for each channel. table 103. descrambler register summary function register name (first occurrence) register bits qty. 1st addr (hex) b1 monitoring disable sonfec_rx_bypass_s0 (r/w) ohp_rx_b1mon_dis 4 01115 b1 monitoring mode sonfec_rx_mode (r/w) rx_b1mon_mode 1 01110 bit/block error control ohp_rx_prov_s0 (r/w) rx_b1bip_mode 4 01310 last second coding violations count ohp_rx_cvs_pm_s0 (ro) rx_cvs 4 01353 function register name (first occurrence) register bits qty. 1st addr (hex) descrambling control sonfec_rx_bypass_s0 (r/w) ohp_rx_descr_dis 4 01115 descrambling mode sonfec_rx_mode (r/w) rx_descr_mode 1 01110
agere systems inc. 133 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 26 transpose demultiplexer 26.1 functional description of the transpose demultiplexer (tdmx) the tdmx macro receives the sts-192 stream in 16-byte blocks. each set of 16 bytes belongs to one of the four possible sts-48 output channels. the macro then outputs bytes for each of the sts-48 channels every clock period. for sts-192 data, the input stream must be demultiplexed to create four sts-48 data streams for further process- ing. the transpose demultiplexer reorders the data so that the sts-192 is divided into its four constituent sts-48 data streams. the byte ordering of the individual sts-1s, or sts-1 components of an sts-nc that comprise the sts-192 as it enters the tdmx and after the tdmx (sts-48 byte ordering), and the details of the sts-192 to sts-48 demulti- plexing, can be found in gr-253-core section 5-1, network element architectural features (multiplexing proce- dure ) page 5-1. if the device is in sts-48 mode, the data is received on all four channels and the tdmx should be bypassed. table 104. transpose demultiplexer register summary function register name (first occurrence) register bits qty. 1st addr (hex) transpose demultiplexer disable control sonfec_rx_tp_bypass (r/w) rx_tdmx_dis 1 01112
134 134 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 27 rdi/ais detection 27.1 functional description of rdi/ais detection the rdi/ais detector in the receive direction detects ais frames prior to bch decoding. if ais is detected, then bch decoding is disabled. in the transmit direction, it detects ais before overhead processing and, if detected, dis- ables bch encoding. rdi in the receive direction is done during overhead processing. table 105. rdi/ais detector register summary note: in 10 gbits/s mode, the master slice (that processes the sts-48 #1 in a sts-192) is slice 3. therefore, though all the rest of the 10 gbits/s alarms are reported in slice 0, in the rdi/ais detector, the alarms in 10 gbits/s are reported at slice 3 registers. f ollowing the same reason, regardless of 10 gbits/s or 2.5 gbits/s mode of operation, all the slices are to be programmed. function register name (first occurrence) register bits qty. 1st addr (hex) ais detection disable control sonfec_rx_bypass_s0 (r/w) ohp_rx_aisd_dis 4 01115 ais detection mode control sonfec_rx_mode (r/w) rx_aisd_mode 1 01110 ais state ohp_rx_sa_state_s0 (ro) rx_ais_l 4 010e8 ais alarm ohp_rx_sa_alarm_s0 (w1c) rx_ais_l_a 4 01024 ais alarm mask ohp_rx_sa_mask_s0 (r/w) rx_ais_l_m 4 01070 ais persistency ohp_rx_sa_persist_s0 (ro) rx_ais_l_p 4 010b8 ais pm ohp_rx_pm_s0 (ro) rx_line_ais_pm 4 0132c rdi state (tx only) ohp_tx_nsa_state_s0 (ro) tx_line_rdi 4 010f4 rdi alarm (tx only) ohp_tx_nsa_alarm_s0 (w1c) tx_line_rdi_a 4 01034 rdi alarm mask (tx only) ohp_tx_nsa_mask_s0 (r/w) tx_line_rdi_m 4 01080 rdi persistency (tx only) ohp_tx_nsa_persist_s0 (ro) tx_line_rdi_p 4 010c4 rdi pm (tx only) ohp_tx_pm_s0 (ro) tx_line_rdi_pm 4 01394
agere systems inc. 135 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 28 b2 monitoring 28.1 functional description of b2 monitoring the line bip-8 is located in each sts-1 of the sts-48, or sts-192, and carries the even parity for the line over- head and spe data within the previous sts-1 frame. the n-line bip-8 bytes in an sts-n are intended to provide a single error monitoring facility for the entire sts-n signal. thus, each b2 monitor block is used to check the 48 line bip-8 codes, whether in sts-48 or sts-192 mode. each bip-8 bit found to be in error causes an internal 22-bit counter to increment. the value in the counter is transferred to the line coding violation (cv-l) registers on the positive edge of the per- formance monitoring clock, at which point the counter is cleared. the counter will stop at the maximum value and will not roll over. when in sts-192 mode, a read of the sts-48 slice 0 cv-l registers returns the 24-bit sum of the four constituent sts-48 channel cv-l counts. therefore, though the registers are 24-bit, in 2.5 gbits/s mode, only the lower 22 bits are valid. in 10 gbits/s mode, only slice 0?s 24 bits are valid, though the maximum count is 0fffffc. during ais insertion due to los, lof, sef, or line ais, processing of the b2 byte is inhibited. it takes five frames of line ais before the actual line ais alarm is declared. once ais insertion is removed, processing of the b2 byte is delayed for two frames. a single b2 controller block collects all the b2 errors and sums up to a single register for 10 gbits/s mode of oper- ation. both transmit and receive b2 monitors are identical. in the receive direction, two b2 monitors are imple- mented before and after bch decoding. these two b2 monitors can be used to compute the coding gain of the decoder. table 106. b2 register summary function register name (first occurrence) register bits qty. 1st addr (hex) b2 monitoring disable (rx only) sonfec_rx_bypass_s0 (r/w) ohp_rx_pre_b2mon_dis 4 01115 b2 monitoring mode (rx only) sonfec_rx_mode (r/w) rx_pre_b2mon_mode 1 01110 coding violations count (rx only) ohp_rx_pre_cvl_l_pm_s0/ ohp_rx_pre_cvl_u_pm_s0 (ro) rx_pre_cvl_l/ rx_pre_cvl_u 40134b/ 0134a b2 monitoring disable (rx only) sonfec_rx_bypass_s0 (r/w) ohp_rx_post_b2mon_dis 4 01115 b2 monitoring mode (rx only) sonfec_rx_mode (r/w) rx_post_b2mon_mode 1 01110 coding violations count (rx only) ohp_rx_post_cvl_l_pm_s0/ ohp_rx_post_cvl_u_pm_s0 (ro) rx_post_cvl_l/ rx_post_cvl_u 4 01342/ 01341 b2 monitoring disable (tx only) sonfec_tx_bypass_s0 (r/w) ohp_tx_b2mon_dis 4 01119 b2 monitoring mode (tx only) sonfec_tx_mode (r/w) tx_b2mon_mode 1 01111 coding violations count (tx only) ohp_tx_cvl_l_pm_s0/ ohp_tx_cvl_l_pm_s0 (ro) tx_cvl_l/ tx_cvl_u 4 0139d/ 0139c
136 136 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 29 ber?sd/sf detection 29.1 functional description of ber?sd/sf detection the line/section bip-8 errors can also be tracked in 16-bit signal fail (sf) and signal degrade (sd) counters. these counters are used to detect sf (signal fail) and sd (signal degrade) conditions for protection switching. the ber threshold for each defect is separately provisionable for each channel over a range of 1 10 ?n values, where n = 3 to 5 for sf and n = 5 to 9 for sd. the detection times and error limits used to detect and clear both defects are dependent on the provisioned ber threshold, as shown in table 107. the sts-192 values shown in the table are the powerup defaults. these values can be changed through the corresponding registers and are common to all channels. the clearing ber threshold for each defect is always 1/10th of the detection threshold. as can be seen in table 107, the range of possible detect thresholds is 1 x 10 ?3 to 1 x 10 ?9 , which results in clear thresholds of 1x10 ?4 to 1 x 10 ?10 . for example, to detect sd at 1 x 10 ?5 ber in an sts-192, the detection time is 4 ms and the detect error limit is 358. the clearing would take place at 1 x 10 ?6 ber, with a clearing time of 6.5 ms and a clear- ing error limit of 77. figure 53 on page 137 illustrates sd detection and clearing using the default sts-192 values specified in table 107. sd thresholds of 1 x 10 ?10 to 1 x 10 ?15 are supported through software. table 107. ber threshold time and error limits for line sd and sf detection in sts-192 mode, the thresholds are compared against the sum of the four sts-48 channel sf and sd counts. a detected sf or sd defect causes a corresponding maskable interrupt status bit to be set in the lte receive slice n service-affecting alarm register. the sd/sf ber control bits in the lte receive channel n maintenance register select the bit error rate for a partic- ular channel. these control bits then select the detection time, detect error limit, and clear error limits for each channel from the lte receive sd/sf registers. the detect error limit and the clear error limit registers contain 16-bit values, while the detection time registers use the lower 15 bits for a value and the upper 1 bit for a time unit specifier. for the detection time register, the value contained in the lower 15 bits is either specified in 0.5 ms units (upper bit = 0) or in seconds (upper bit = 1). note that the performance monitoring clock input to the device is used as the timing reference when the detection time is expressed in seconds. the sd/sf ber select control bits are described in table 108 and table 109 on page 138. a fixed windowing scheme is used for sd/sf detection. the window size is determined by the value in the detec- tion time register for the specified bit error rate. an sd or sf alarm is declared immediately when the accumulated error count exceeds the value specified in the detect error limit register. in the detection process, when the error count equals the threshold, the window is prematurely ended and clearing process starts immediately. if this error limit is not reached by the end of the window, then the accumulated error count is reset to zero. when an sd or sf alarm is declared, the accumulated error count resets and clearing begins using the bit error rate threshold that is 1/10th of the specified value along with the corresponding detection time registers. clearing of the sd or sf alarm only occurs at the end of the window when the accumulated error count is less than the value specified in the clear error limit register. ber threshold detection time detect error limit clear error limit sts-48 sts-192 sts-48 sts-192 sts-48 sts-192 1 10 ?3 4 ms 4 ms 4818 19453 ? ? 1 10 ?4 4 ms 4 ms 862 3543 957 3734 1 10 ?5 4 ms 4 ms 81 358 114 423 1 10 ?6 31 ms 6.5 ms 62 51 91 77 1 10 ?7 312.5 ms 65 ms 62 51 91 77 1 10 ?8 2600 ms 650 ms 51 51 77 77 1 10 ?9 21 s 5250 ms 40 40 63 63 1 10 ?10 170 s 41 s ? ? 52 51
agere systems inc. 137 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 29 ber?sd/sf detection (continued) 29.1 functional description of ber?sd/sf detection (continued) the sonfec incorporates two sd/sf detectors in the receive direction. these two monitors can be used as a measurement for the coding gain. the pre-sd/sf detector monitors the b1 or b2 errors for sd/sf detection before bch decoding. the post-sd/sf detector monitors the b2 errors after bch decoding. figure 53. example of sts-192 sd detection (10 ?5 ber) and clearing (10 ?6 ber) during ais, insertion due to los, lof, sef, or line ais, processing of the b2 byte is inhibited and the internal sf/sd counters are reset back to zero. it takes 5 frames of line ais before the actual line ais alarm is declared; it is likely that the signal degrade alarm will also be triggered. due to this fact, once ais insertion is removed, pro- cessing of the sd/sf is delayed for 2 frames. table 108. sd ber select control note: see table 110, b2 register summary, on page 138 for rx_pre_sd_ber_sel and for rx_post_sd_ber_sel descriptions. register bits value description rx_pre_sd_ber_sel/ rx_post_sd_ber_sel 000 select ber 1 x 10 ?5 . 001 select ber 1 x 10 ?6 . 010 select ber 1 x 10 ?7 . 011 select ber 1 x 10 ?8 . 100 select ber 1 x 10 ?9 . others select ber 1 x 10 ?5 . sd accumulated b2 errors time (ms) 358 77 48 6 12.5 19 sd detected sd cleared sd detection window sd clearing window
138 138 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 29 ber?sd/sf detection (continued) 29.1 functional description of ber?sd/sf detection (continued) table 109. sf ber select control note: see table 110 for rx_pre_sf_ber_sel and for rx_post_sf_ber_sel descriptions. table 110. b2 register summary 30 receive transport overhead processing 30.1 functional description of the receive transport overhead processing this block terminates the transport overhead and incorporates four identical sts-48 overhead processing blocks. each block accepts the frame and byte-aligned data for one sts-48 channel and extracts the transport section and line overhead. the extracted overhead is then either stored internally or provided externally on a serial output, and may also be further processed for alarm or performance monitoring purposes. the received overhead bytes can also be allowed to pass through unchanged. the definition and associated storage or processing of each byte is detailed in the following subsections. all processing of overhead bytes is inhibited under ais conditions. an ais frame can be generated either by hard- ware or software. register bits value description rx_pre_sf_ber_sel/ rx_post_sf_ber_sel 00 select ber 1 x 10 ?3 . 01 select ber 1 x 10 ?4 . 10 select ber 1 x 10 ?5 . others select ber 1 x 10 ?3 . function register name (first occurrence) register bits qty. 1st addr (hex) sd/sf detection time (1 x 10 ?3 ) 1 1. these registers are the highest ber. lower ber configuration registers directly follow these, in secession. ohp_rx_sdsf_dt3 (r/w) rx_sdsf_dt_unit_3 rx_sdsf_dt_val_3 8 01220 sd/sf detect error limit (1 x 10 ?3 ) 1 ohp_rx_sdsf_set3 (r/w) rx_sdsf_set_limit_3 7 01250 sd/sf clear error limit (1 x 10 ?4 ) 1 ohp_rx_sdsf_clr4 (r/w) rx_sdsf_clr_limit_4 7 01280 pre sd/sf bip select ohp_rx_maint_s0 (r/w) rx_pre_sd_sf_bipsel 4 01318 sd/sf threshold selection ohp_rx_maint_s0 (r/w) rx_pre_sd_ber_sel rx_pre_sf_ber_sel 4 01318 sd/sf interrupt alarms ohp_rx_sa_alarm_s0 (w1c) rx_pre_sd_a rx_pre_sf_a 4 01024 sd/sf interrupt masks ohp_rx_sa_mask_s0 (r/w) rx_pre_sd_m rx_pre_sf_m 4 01070 sd/sf state ohp_rx_sa_state_s0 (ro) rx_pre_sd rx_pre_sf 4 010e8 sd/sf persistency ohp_rx_sa_persist_s0 (ro) rx_pre_sd_p rx_pre_sf_p 4 010b8
agere systems inc. 139 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 30 receive transport overhead processing (continued) 30.1 functional description of the receive transport overhead processing (continued) table 111. hardware ais generation summary (receive) in addition to the individual storage or external availability of the overhead bytes described below, the transport overhead bytes for each sts-48 (individual or part of sts-192) are serialized and output on the toac pins of the device. there are four sets of toac data pins available for each sts-48 channel. this toac interface can oper- ate in two modes 1 . in full toac drop mode, the full set of transport overhead bytes for each sts-48 channel (1296 bytes) is output on the toac pins. in partial toac drop mode, only the transport overhead bytes of the first sts-1 of each sts-48 channel (27 bytes) are output on the toac pins. the bytes are output, msn (most signifi- cant nibble) first (4 bits on 4 pins), with each bit output on the positive edge of the toac clock (20.736 mhz (full)/ 1.728 mhz (partial)). the location of the msn of the first a1 byte is identified by the toac sync output going high. in sts-48 mode, each of the toac data pins transmits the transport overhead for an sts-48 channel. in sts-192 (full toac) mode, the four pairs of the toac data pins transmit the sts-192 overhead (5184 bytes), where the toac data #1 pins transmit sts channels 1 through 48, and the toac data #2, toac data #3, and toac data #4 pins transmit sts channels 49 through 96, 97 through 144, and 145 through 192, respectively. the receive toac drop is described in detail in section 32.1 on page 160. note: in sonfec, four overhead processors capable of processing an entire sts-48 are implemented. in 2.5 gbits/s mode, each functions independently. however, in 10 gbits/s mode, only one slice (that process the sts-48 #1 in a sts-192) functions as master slice and the others function very minimally. in ohp, this master slice is slice 3. therefore, though all the rest of the 10 gbits/s alarms are reported in slice 0, in ohp, the alarms in 10 gbits/s are reported in the slice 3 registers. following the same reason, regardless of 10 gbits/s or 2.5 gbits/s mode of operation, all the overhead processing slices are to be programmed. 30.1.1 global overhead byte processing insertion of ais on the receive side can be either due to hardware or software. if hardware ais is detected, then the overhead bytes, except a1 and a2, are set to 0xff. a1 bytes and a2 bytes will have the inserted framing pat- tern. in the following sections, the term rx_hw_insert_ais is used to indicate a hardware controlled ais condition. the register bit receive sdh mode controls the default values of overhead bytes. if set to 1, the default overhead values are set to 0ff (sdh mode); otherwise, it is set to 000 (sonet mode). table 112. receive overhead processor general register summary ais generation alarms ais generation disables description rx_loc_a ? loss of clock. rx_los_a ? loss of signal. rx_sef_a rx_sef_ais_dis detected severely errored frame. rx_lof_a rx_lof_ais_dis detected loss of frame. rx_ais_l_a rx_line_ais_dis detected line ais frame. rx_j0_mismatch_a rx_tim_l_ais_dis detected j0 mismatch. rx_post_sf_a rx_sf_ais_dis detected signal fail. 1. for more information on the two toac modes, see section 2.4, toac insert/drop channel overview, on page 10. function register name (first occurrence) register bits qty. 1st addr (hex) sonet/sdh mode ohp_rx_prov_s0 (r/w) rx_sdh_mode 4 01310 ohp mode control sonfec_rx_mode (r/w) rx_ohp_mode 1 01110 ais-l insert control ohp_rx_maint_s0 (r/w) rx_line_ais_ins 4 01314
140 140 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 30 receive transport overhead processing (continued) 30.1 functional description of the receive transport overhead processing (continued) 30.1.1.1 default all undefined bytes in section overhead for all the bytes that are not specified in the following sections, and default bytes in other sts-1(s) in a sts-48 or sts-192, processing is done as follows: if not (rx_hw_insert_ais) section_undefined_byte = received_line_data; else section_undefined_byte = default_sonet_sdh; end 30.1.1.2 default all undefined bytes in line overhead for all the bytes that are not specified in the following sections, and default bytes in other sts-1(s) in a sts-48 or sts-192, processing is done as follows: if (rx_line_ais_ins) or (rx_hw_insert_ais) line_undefined_byte = 0xff; else line_undefined_byte = received_line_data; end 30.1.1.3 framing byte (a1) the framing byte a1 is overwritten if not inhibited by software. if normal framing is selected, the a1 bytes are set to 0xf6, while the a2 bytes are set to 0x28. if enhanced framing is selected, using the framing mode control bit, the a1 bytes and a2 bytes contain normal framing (0xf6 and 0x28) in odd sts-1 time slots and the inverse value (0x09 and 0xd7) in even sts-1 time slots. if (rx_a1a2_inh) and not (rx_hw_insert_ais) a1 = received_line_data; else if (rx_enh_frmg_ins) a1 = enhanced_framing_a1; else a1 = normal_framing_a1; end table 113. a1 register summary (receive) function register name (first occurrence) register bits qty. 1st addr (hex) a1 insertion enable ohp_rx_prov_s0 (r/w) rx_a1a2_inh 4 01310 enhanced framing rx_enh_frmg_ins 4 01310
agere systems inc. 141 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 30 receive transport overhead processing (continued) 30.1 functional description of the receive transport overhead processing (continued) 30.1.1.4 framing byte (a2) the framing byte a2 is overwritten if not inhibited by software. if normal framing is selected, the a1 bytes are set to 0xf6, while the a2 bytes are set to 0x28. if enhanced framing is selected using the framing mode control bit, the a1 bytes and a2 bytes contain normal framing (0xf6 and 0x28) in odd sts-1 time slots and the inverse value (0x09 and 0xd7) in even sts-1 time slots. if (rx_a1a2_inh) and not (rx_hw_insert_ais) a2 = received_line_data; else if (rx_enh_frmg_ins) a2 = enhanced_framing_a2; else a2 = normal_framing_a2; end table 114. a2 register summary (receive) 30.1.1.5 section trace (j0) the section trace byte is present in the first sts-1 of the sts-48 or sts-192 only. specified by the j0 message type control bit, the toh processor supports extraction of either sonet 64-byte (ascii, terminated) or sdh 16-byte (e.164) section trace messages which are stored in internal memory. processing of the received message then depends on the j0 message mode control bit. the content of the message is either monitored for a mismatch from a provisioned expected message, or monitored for a sustained change (validation) in the received message. table 115. j0 message control register bits (receive) note: see table 116 for rx_j0_type and rx_j0_mode descriptions. if the j0 message mode control bit is set to the provisioned mode, then the incoming message is compared against the software programmed expected message. the expected message is stored in the internal memory for each sts-48 channel. a mismatch is declared if a consistent received message differs from the expected message for ten consecutive messages. the mismatch clears when four out of five received messages match the expected message (fixed windowing is used for clearing). this mismatch state is reflected in the j0 message mismatch alarm bit. if j0 mismatch is detected, it can optionally generate ais frames if software enabled. function register name (first occurrence) register bits qty. 1st addr (hex) a2 insertion enable ohp_rx_prov_s0 (r/w) rx_a1a2_inh 4 01310 enhanced framing rx_enh_frmg_ins 4 01310 register bits value description rx_j0_type 0 sonet format (64 byte). 1 sdh format (16 byte). rx_j0_mode 01 provisioned (expected value). 10 validated (sustaining value). 11/00 undefined.
142 142 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 30 receive transport overhead processing (continued) 30.1 functional description of the receive transport overhead processing (continued) when the j0 message mode control bit is set to the validated mode, the incoming message is monitored for a sus- tained change. a sustained change is detected when the received message differs from the last stable message for ten consecutive messages. the new message then becomes the stable message, is stored in internal memory, and the processor starts checking for a sustained change from this new stable message (i.e., there is no clearing criteria for a sustained change). the j0 new message alarm bit is set when a sustained change is detected. selection of the message type, sonet or sdh format, and the content monitoring mode (provisioned or vali- dated), are provisionable on a per sts-48 channel basis through a corresponding lte receive channel mainte- nance register. the associated alarms for the two modes are reported in the corresponding lte receive channel nonservice affecting interrupt alarm register. the expected messages for all channels are provisioned through the microprocessor interface using the 64-byte j0 access expected message buffer. the sustained or captured messages for all channels are available through the microprocessor interface, using the 64-byte j0 access received message buffer. if not (rx_hw_insert_ais) j0 = received_line_data; else j0 = 0ff; end table 116. j0 register summary (receive) function register name (first occurrence) register bits qty. 1st addr (hex) message type control ohp_rx_maint_s0 (r/w) rx_j0_type rx_j0_mode 4 1318 message mismatch alarm ohp_rx_nsa_0_alarm_s0 (w1c) rx_j0_mismatch_a 4 0102c new message alarm ohp_rx_nsa_1_alarm_s0 (w1c) rx_j0_new_a 4 01028 message mismatch alarm mask ohp_rx_nsa_0_mask_s0 (r/w) rx_j0_mismatch_m 4 01078 new message alarm mask ohp_rx_nsa_1_mask_s0 (r/w) rx_j0_new_m 4 01074 message mismatch state ohp_rx_nsa_0_state_s0 (ro) rx_j0_mismatch 4 010ec message mismatch persistency ohp_rx_nsa_0_persist_s0 (ro) rx_j0_mismatch_p 4 010bc j0 access expected message buffer ohp_rx_j0exp0_s0 ohp_rx_j0exp31_s0 (r/w) rx_j0_exp_0 rx_j0_exp_31 [32] 401800 0181f j0 access sustained message buffer ohp_rx_j0sus0_s0 ohp_rx_j0sus31_s0 (ro) rx_j0_sus_0 rx_j0_sus_31 [32] 401880 0189f
agere systems inc. 143 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 30 receive transport overhead processing (continued) 30.1 functional description of the receive transport overhead processing (continued) 30.1.1.6 section growth (z0) no receive function has been defined for the section growth byte present in the remaining sts-1 locations of the sts-48 or sts-192 j0 byte. in the receive direction, these bytes are transferred to the system interface or toac drop without modification. if not (rx_hw_insert_ais) z0 = received_line_data; else z0 = 0ff; end 30.1.1.7 section bip-8 (b1) the section bip-8 b1 byte is located in the first sts-1 of the sts-48 or sts-192 only. the computed b1 is inserted on the first sts-1 b1 byte location. the other sts-1 b1 bytes are transferred to the system interface or toac drop without modification. optionally, b1 can be corrupted by enabling the b1 corrupt enable bit. b1 insertion is con- trolled by b1 compute block. the overhead processor bypasses the received b1. 30.1.1.8 local orderwire (e1) the local orderwire byte is located in the first sts-1 of the sts-48 or sts-192 only and provides a 64 khz channel for voice communications between regenerators, hubs, and remote terminals. these bytes are transferred to the system interface or toac drop without modification. if not (rx_hw_insert_ais) e1 = received_line_data; else e1 = 0ff; end
144 144 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 30 receive transport overhead processing (continued) 30.1 functional description of the receive transport overhead processing (continued) 30.1.1.9 section user channel (f1) the section user channel byte is located in the first sts-1 of the sts-48 or sts-192 only and provides a 64 khz channel for use by the network provider. the byte is extracted from each frame. a new value is only validated and stored in the f1 byte after it has been received for the programmed n consecutive times. detection of a new vali- dated byte is indicated by the f1 new byte alarm bit. the alarm is only generated when the value of the new vali- dated byte is different from the value of the last validated byte. the other sts-1 f1 bytes are transferred to the system interface or toac drop without modification. if not (rx_hw_insert_ais) f1 = received_line_data; else f1 = 0ff; end table 117. section user channel (f1) register summary 30.1.1.10 section data communications channel (d1, d2, and d3) the section data communications channel bytes are located in the first sts-1 of the sts-48 or sts-192 only and are used as one 192 khz message-based channel for operations, administration, and maintenance (oa&m) com- munication. these bytes are transferred to the system interface or toac drop without modification. if not (rx_hw_insert_ais) d1_to_d3 = received_line_data; else d1_to_d3 = 0ff; end 30.1.1.11 line bip-8 (b2) the line bip-8 b2 byte is provided in all the sts-1s of the sts-48 or sts-192. the computed b2 is inserted in these locations. optionally, b2 can be corrupted by enabling the b2 corrupt enable bit. if (rx_line_ais_ins) or (rx_hw_insert_ais) b2 = 0xff; else b2 = computed_b2; end function register name (first occurrence) register bits qty. 1st addr (hex) new validated f1 alarm ohp_rx_nsa_1_alarm_s0 (w1c) rx_f1_new_a 4 01028 new validated f1 alarm mask ohp_rx_nsa_1_mask_s0 (r/w) rx_f1_new_m 4 01074 new validated f1 value ohp_rx_f1s1byte_s0 (ro) rx_f1_byte 4 01334 validated f1 n-time detect ohp_rx_f1s1det_s0 (r/w) rx_f1_ndet 4 01328
agere systems inc. 145 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 30 receive transport overhead processing (continued) 30.1 functional description of the receive transport overhead processing (continued) 30.1.1.12 sts payload pointer (h1, h2, and h3) the sts pointers are passed through unchanged. if prbs payload monitoring is enabled, these pointer values are set to 522 1 . these bytes are transferred to the system interface or toac drop without modification. if (rx_line_ais_ins) or (rx_hw_insert_ais) h1_to_h3 = 0xff; else h1_to_h3 = received_line_data; end 30.1.1.13 receive aps channel (k1 and k2) the aps channels? bytes are located in the first sts-1 of the sts-48 or sts-192 only, and are used for automatic protection switching (aps) signaling to coordinate line-level protection switching. in addition, the k2 byte is also used to carry line ais (ais-l) and line rdi (rdi-l) signals. the other sts-1 k1/k2 bytes are transferred to the system interface or toac drop without modification. a new value in either byte is only validated after it has been received n times consecutively, where n is provision- able to 3 or 5 using the k1k2 validate select control bit. when a k1 or k2 byte is validated, the value is stored in the k byte status register and the k1k2 new byte alarm bit is set. these two alarms are only generated when the value of the new validated k1 or k2 byte is different from the value of the last validated byte. validation of the k1 and k2 bytes, and the generation of the alarms, is not affected by the line ais status. the validated k1 and k2 bytes are further processed for the following defects: protection switching byte. this defect occurs when either an inconsistent aps byte or an invalid code is detected. an inconsistent aps byte occurs when no n consecutive k1 bytes of the last twelve successive frames are identical, starting with the last frame containing a previously consistent byte. an invalid code occurs when the incoming k1 byte contains an unused code or a code irrelevant for the specific switching operation in three con- secutive frames. an invalid code also occurs when the incoming k1 byte contains an invalid channel number in three consecutive frames. because invalid code detection requires information not readily available to hardware, it must be detected by software polling of the validated k1 byte value. an inconsistent aps byte defect is detected by hardware and will cause an alarm status bit to be set in the corresponding lte receive channel non- service-affecting interrupt alarm register. it is cleared when a k1 byte is received and validated. an inconsistent aps byte defect is neither detected nor terminated during an ais-l defect. processing of the inconsistent aps byte defect is also inhibited when the validated k1 byte has a value of 0xff and bits 2?0 of the validated k2 byte have a value of 111 (line ais). this additional feature prevents a change in the inconsistent aps defect state just before line ais is declared. channel mismatch. this defect occurs when the channel numbers in the transmitted k1 byte (bits 3?0) and the validated received k2 byte (bits 7?4) are not identical. detection of a channel mismatch defect causes a latched alarm status bit to be set in the corresponding lte receive channel nonservice-affecting interrupt alarm register. a channel mismatch defect is neither detected nor terminated during an ais-l defect. processing of the channel mismatch defect is also inhibited when the validated k2 byte has a value of 1111x111 binary. this additional fea- ture prevents a change in the channel mismatch defect state just before line ais is declared. 1. the pointer is set by the incoming signal. only when prbs data is injected into the sonet frame is the pointer set, by the de vice, to 522.
146 146 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 30 receive transport overhead processing (continued) 30.1 functional description of the receive transport overhead processing (continued) in addition, the currently received k2 byte is processed for the following defects: line ais (ais-l). declared when bits 2?0 of k2 contain 111 for five consecutive frames. cleared when any other pattern is received for five consecutive frames. detection of a line ais defect is indicated by an alarm status bit, a persistency bit, and a 1 s pm bit being set in the registers for the affected channel. line rdi (rdi-l). declared when bits 2?0 of k2 contain 110 (binary) for five consecutive frames. cleared when any other pattern is received for five consecutive frames. detection of a line rdi defect is indicated by a latched alarm status bit and a 1 s pm bit being set in the registers for the affected channel. if (rx_line_ais_ins) or (rx_hw_insert_ais) k1_to_k2 = 0xff; else k1_to_k2 = received_line_data; end table 118. aps channel (k1 and k2) register summary (receive) function register name (first occurrence) register bits qty. 1st addr (hex) k1k2 validation length select (3 or 5) ohp_rx_prov_s0 (r/w) rx_k_val_limit_sel 4 01310 validated k1k2 storage ohp_rx_k1k2byte_s0 (ro) rx_k1_byte rx_k2_byte 4 01330 new validated k1k2 alarm ohp_rx_nsa_1_alarm_s0 (w1c) rx_k1_new_a rx_k2_new_a 4 01028 inconsistent aps alarm ohp_rx_nsa_0_alarm_s0 (w1c) rx_inconsistent_aps_a 4 0102c channel mismatch alarm ohp_rx_nsa_0_alarm_s0 (w1c) rx_k1k2ch_mismatch_a 4 0102c new validated k1k2 alarm mask ohp_rx_nsa_1_mask_s0 (w1c) rx_k1_new_m rx_k2_new_m 4 01074 inconsistent aps alarm mask ohp_rx_nsa_0_mask_s0 (r/w) rx_inconsistent_aps_m 4 01078 channel mismatch alarm mask ohp_rx_nsa_0_mask_s0 (r/w) rx_k1k2ch_mismatch_m 4 01078 rdi-l alarm ohp_rx_nsa_0_alarm_s0 (w1c) rx_line_rdi_a 4 0102c rdi-l alarm mask ohp_rx_nsa_0_mask_s0 (r/w) rx_line_rdi_m 4 01078 last second rdi-l pm ohp_rx_pm_s0 (ro) rx_line_rdi_pm 4 0132c inconsistent aps state ohp_rx_nsa_0_state_s0 (ro) rx_inconsistent_aps 4 010ec channel mismatch state ohp_rx_nsa_0_state_s0 (ro) rx_k1k2ch_mismatch 4 010ec inconsistent aps persistency ohp_rx_nsa_0_persist_s0 (ro) rx_inconsistent_aps_p 4 010ec channel mismatch persistency ohp_rx_nsa_0_persist_s0 (ro) rx_k1k2ch_mismatch_p 4 010bc rdi-l state ohp_rx_nsa_0_state_s0 (ro) rx_line_rdi 4 010ec rdi-l persistency ohp_rx_nsa_0_persist_s0 (ro) rx_line_rdi_p 4 010bc
agere systems inc. 147 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 30 receive transport overhead processing (continued) 30.1 functional description of the receive transport overhead processing (continued) 30.1.1.14 line data communication channel (d4?d12) the line data communication channel bytes are located in the first sts-1 of the sts-48 or sts-192 only and are used as one 576 khz message-based channel for operations, administration, and maintenance communication (oa & m). these bytes are transferred to the system interface or toac drop without modification. if (rx_line_ais_ins) or (rx_hw_insert_ais) d4_to_d12 = 0xff; else d4_to_d12 = received_line_data; end 30.1.1.15 synchronization status (s1) the synchronization status byte is located in the first sts-1 of the sts-48 or sts-192 only and is used to convey the synchronization status of a network element. the byte is extracted from each frame. a new value is only vali- dated and stored in the s1 byte after it has been received for the programmed n consecutive times. detection of a new validated byte is indicated by the s1 new byte alarm bit. the alarm is only generated when the value of the new validated byte is different from the value of the last validated byte. the other sts-1 s1 bytes are transferred to the system interface or toac drop without modification. if (rx_line_ais_ins) or (rx_hw_insert_ais) s1 = 0xff; else s1 = received_line_data; end table 119. receive synchronization status (s1) register summary function register name (first occurrence) register bits qty. 1st addr (hex) new validated s1 alarm ohp_rx_nsa_1_alarm_s0 (w1c) rx_s1_new_a 4 01028 new validated s1 alarm mask ohp_rx_nsa_1_mask_s0 (r/w) rx_s1_new_m 4 01074 new validated s1 value ohp_rx_f1s1byte_s0 (ro) rx_s1_byte 4 01334 validated s1 n-time detect ohp_rx_f1s1det_s0 (r/w) rx_s1_ndet 4 01328
148 148 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 30 receive transport overhead processing (continued) 30.1 functional description of the receive transport overhead processing (continued) 30.1.1.16 line remote error indication (m1) the line remote error indication (rei-l) byte is located in the third sts-1 of the sts-48 or sts-192 only (in order of appearance in the sts-192 signal) and is used to convey to the far end the number of errors detected using the line bip-8 bytes (truncated at 255). the byte is extracted from each frame and the value added to an internal 21-bit counter. the value in the counter is transferred to the rei-l registers on the positive edge of the performance mon- itoring (pm) clock input, at which point the counter is cleared. the counter will stop at the maximum value and will not roll over. the other sts-1 m1 bytes are transferred to the system interface or toac drop without modification. if (rx_line_ais_ins) or (rx_hw_insert_ais) m1 = 0xff; else m1 = received_line_data; end table 120. line rei (m1) register summary 30.1.1.17 express orderwire (e2) the express orderwire byte is located in the first sts-1 of the sts-48 or sts-192 only and provides a 64 khz channel for voice communications between line entities. the other sts-1 e2 bytes are transferred to the system interface or toac drop without modification. if (rx_line_ais_ins) or (rx_hw_insert_ais) e2 = 0xff; else e2 = received_line_data; end 31 transmit transport overhead (toh) processor 31.1 functional description of toh processor this block inserts the transport overhead and incorporates four identical sts-48 overhead processing blocks. each block accepts the data for one sts-48 channel from the transmit payload add interface and inserts the trans- port section and line overhead. the inserted overhead is either sourced internally or provided externally on serial inputs. if sourced internally, the overhead may be from registers in the microprocessor interface, or derived. the received overhead bytes can also be allowed to pass through unchanged. in sts-48 mode, each channel carries complete transport overhead. in sts-192 mode, only the first sts-48 chan- nel carries complete transport overhead, while the other channels only carry framing (a1, a2), z0, and line bip-8. in addition, the line overhead bytes can all be overwritten with all ones (along with all of the payload spe bytes) by enabling line ais insertion. if software is disabled, the transmit overhead processing is disabled. software can dis- able either the line overhead bytes processing, section overhead bytes processing, or both. all processing of overhead bytes is inhibited under ais conditions. an ais frame can be generated either by hard- ware or software. function register name (first occurrence) register bits qty. 1st addr (hex) last second rei-l count ohp_rx_rei_l_pm_s0 ohp_rx_rei_u_pm_s0 (ro) rx_reil_u rx_reil_l 4 4 01338 01339
agere systems inc. 149 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 31 transmit transport overhead (toh) processor (continued) 31.1 functional description of toh processor (continued) table 121. hardware ais generation summary (transmit) in addition to the individual storage or external availability of the overhead bytes described, the transport overhead bytes for each sts-48 (individual or part of sts-192) can be sourced serially using the toac data pins. this toac interface can operate in two modes 1 . in full toac drop mode, the full set of transport overhead bytes for each sts-48 channel (1296 bytes) can be sourced on the toac pins. in partial toac drop mode, only the trans- port overhead bytes of the first sts-1 of each sts-48 channel (27 bytes) can be sourced on the toac pins. inser- tion must be globally enabled through software using the toh data insert control bit, and then enabled on a per- byte basis by strobing the toac enable pin high during the lsb of the byte to insert (the state of the toac enable is ignored during the other bits). the bytes are received, msn (most significant nibble) first (4 bits on 4 pins), with each bit output on the positive edge of the toac clock (20.736 mhz (full)/1.728 mhz (partial)). the location of the msn (most significant nibble) bit of the first a1 byte is identified by the toac sync output going high. for b2, the value received is actually used as an xor corruption mask for the internally calculated values. in sts-48 mode, the individual toac data pins, along with the toac enable pin, capture the transport overhead for that sts-48 channel. in sts-192 mode, the four pairs of toac data pins, along with their respective toac enable pins, capture the entire sts-192 overhead (5184 bytes), where the toac data #1 pins capture sts chan- nels 1 through 48, and the toac data #2, toac data #3, and toac data #4 pins capture sts channels 49 through 96, 97 through 144, and 145 through 192, respectively. the toac insert functionality is described in detail later in this section. note: in sonfec, four overhead processors capable of processing an entire sts-48 are implemented. in 2.5 gbits/s mode, each functions independently. however, in 10 gbits/s mode, only one slice (that process the sts-48 #1 in an sts-192) functions as a master slice and all others functions are very minimal. in ohp, the master slice is slice 3. therefore, though all the rest of the 10 gbits/s alarms are reported in slice 0, in overhead processor, the alarms in 10 gbits/s are reported at slice 3 registers. following the same reason, regardless of 10 gbits/s or 2.5 gbits/s mode of operation, all the overhead processing slices are to be pro- grammed. ais generation alarms ais generation disables description tx_loc_a ? loss of clock. tx_los_a ? loss of signal. tx_sef_a tx_sef_ais_dis detected severely errored frame. tx_lof_a tx_lof_ais_dis detected loss of frame. tx_ais_l_a tx_line_ais_dis detected line ais frame. 1. for more information on the two toac modes, see section 2.4 on page 10.
150 150 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 31 transmit transport overhead (toh) processor (continued) 31.1 functional description of toh processor (continued) 31.1.1 global overhead byte insertion if toac insertion is enabled, the first 2 bits (msb and msb ? 1 positions of the data) of the toac data enable input control the overhead byte insertion. table 122. toac byte insertion control in the following sections, the term toac_controlled_data is used to indicate the data inserted in the overhead byte position, depending on the toac enable pin. if ais is detected, then all the line overhead bytes are set to 0xff. insertion of ais can be either due to hardware or software. in the following sections, the term tx_hw_insert_ais is used to indicate a hardware-controlled ais condition. the register bit transmit sdh mode controls the default values of overhead bytes. if set to 1, the default value is set to either 0xff (sdh mode) or 0x00 (sonet mode). table 123. transmit overhead processor general register summary 31.1.1.1 default all undefined bytes in section overhead for all the bytes that are not specified in the following sections and default bytes in other sts-1(s) in an sts-48 or sts-192, processing is done as follows: if (tx_toac_enb) section_undefined_byte = toac_controlled_data; else if (ohp_tx_soh_proc_dis) and not (tx_hw_insert_ais) section_undefined_byte = received_system_data; else section_undefined_byte = default_sonet_sdh; end toac enable data value description tx_toac_enb (pin) sampled at [msb], [msb ? 1] positions only 11 insert data from the serial toac input. 00 default data. 01 bypass data. 10 software controlled data. function register name (first occurrence) register bits qty. 1st addr (hex) ohp (soh) disable control sonfec_tx_bypass_s0 (r/w) ohp_tx_soh_proc_dis 4 01119 ohp (loh) disable control sonfec_tx_bypass_s0 (r/w) ohp_tx_loh_proc_dis 4 01119 global toac byte insert control ohp_tx_prov_s0 (r/w) tx_toac_enb 4 01370 sonet/sdh mode ohp_tx_prov_s0 (r/w) tx_sdh_mode 4 01370 ohp mode control sonfec_tx_mode (r/w) tx_ohp_mode 1 01111 ais-l insert control ohp_tx_maint_s0 (r/w) tx_line_ais_ins 4 01374
agere systems inc. 151 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 31 transmit transport overhead (toh) processor (continued) 31.1 functional description of toh processor (continued) 31.1.1.2 default all undefined bytes in line overhead for all the bytes that are not specified in the following sections and default bytes in other sts-1(s) in an sts-48 or sts-192, processing is done as follows: if (tx_line_ais_ins) or (tx_hw_insert_ais) line_undefined_byte = 0xff; else if (tx_toac_enb) line_undefined_byte = toac_controlled_data; else if (ohp_tx_loh_proc_dis) line_undefined_byte = received_system_data; else line_undefined_byte = default_sonet_sdh; end 31.1.1.3 framing byte (a1) the framing byte a1 is overwritten if not inhibited by software. if normal framing is selected, the a1 bytes are set to 0xf6, while the a2 bytes are set to 0x28. if enhanced framing is selected using the framing mode control bit, the a1 bytes and a2 bytes contain normal framing (0xf6 and 0x28) in odd sts-1 time slots and the inverse value (0x09 and 0xd7) in even sts-1 time slots. if (tx_toac_enb) a1 = toac_controlled_data; else if (tx_a1a2_inh) and not (tx_hw_insert_ais) a1 = received_system_data; else if (tx_enh_frmg_ins) a1 = enhanced_framing_a1; else a1 = normal_framing_a1; end table 124. a1 register summary (transmit) function register name (first occurrence) register bits qty. 1st addr (hex) a1 insertion enable ohp_tx_prov_s0 (r/w) tx_a1a2_inh 4 01370 enhanced framing tx_enh_frmg_ins 4 01370
152 152 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 31 transmit transport overhead (toh) processor (continued) 31.1 functional description of toh processor (continued) 31.1.1.4 framing byte (a2) the framing byte a2 is overwritten if not inhibited by software. if normal framing is selected, the a1 bytes are set to 0xf6, while the a2 bytes are set to 0x28. if enhanced framing is selected using the framing mode control bit, the a1 bytes and a2 bytes contain normal framing (0xf6 and 0x28) in odd sts-1 time slots and the inverse value (0x09 and 0xd7) in even sts-1 time slots. alternatively, errors can be inserted in a2 bytes by setting the corre- sponding tx_a2_err_ins bit for each slice. the errors are inserted by inverting every fourth a2 byte out of the 192 a2 bytes starting with the first byte. also, during a2 error insertion, normal framing is always used even if tx_enh_frmg_ins is set to 1. if (tx_toac_enb) a2 = toac_controlled_data; else if (tx_a2_err_ins) a2 = errored_a2; else if (tx_a1a2_inh) and not (tx_hw_insert_ais) a2 = received_system_data; else if (tx_enh_frmg_ins) a2 = enhanced_framing_a2; else a2 = normal_framing_a2; end table 125. a2 register summary (transmit) 31.1.1.5 section trace (j0) the section trace byte is present in the first sts-1 of the sts-48 or sts-192 only. the toh processor supports insertion of either sonet 64-byte (ascii, terminated) or sdh 16-byte (e.164) section trace mes- sages. the message is stored in internal memory and should be repeated four times if a 16-byte sdh message is to be sent. the message is provisioned by software using the section trace access registers. after the message is provisioned, insertion of the message must be enabled through the j0 message insert control bit. if insertion is not enabled, the j0 byte is instead sent as 0x01 for sts-48/sts-192 mode. if (tx_toac_enb) j0 = toac_controlled_data; else if (tx_j0_ins) j0 = mpu_programmed_j0; else if (ohp_tx_soh_proc_dis) and not (tx_hw_insert_ais) j0 = received_system_data; else j0 = 001; end function register name (first occurrence) register bits qty. 1st addr (hex) a2 insertion enable ohp_tx_prov_s0 (r/w) tx_a1a2_inh 4 01370 enhanced framing ohp_tx_prov_s0 (r/w) tx_enh_frmg_ins 4 01370 a2 error control ohp_tx_maint_s0 (r/w) tx_a2_err_ins 4 01378
agere systems inc. 153 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 31 transmit transport overhead (toh) processor (continued) 31.1 functional description of toh processor (continued) table 126. j0 register summary (transmit) 31.1.1.6 section growth (z0) the section growth bytes are present in the sts-1 locations, excluding the first sts-1 of the sts-48 or sts-192. they are set to the fixed pattern 0xcc in sts-192 mode, or to an increasing binary count (2 to 48, corresponding to order of appearance) in sts-48 mode. if (tx_toac_enb) z0 = toac_controlled_data; else if (ohp_tx_soh_proc_dis and not (tx_hw_insert_ais) z0 = received_system_data; else if (tx_ohp_mode equals 2g5) z0 = 002_to_048; else z0 = 0cc; end 31.1.1.7 section bip-8 (b1) the section bip-8 b1 byte is located only in the first sts-1 of the sts-48 or sts-192. the computed b1 is inserted on the first sts-1 b1 byte location. optionally, b1 can be corrupted by enabling the b1 corrupt enable bit. if (tx_toac_enb) b1 = toac_controlled_data; else if (ohp_tx_soh_proc_dis) and not (tx_hw_insert_ais) b1 = received_system_data; else b1 = default_sonet_sdh; end function register name (first occurrence) register bits qty. 1st addr (hex) message insert control ohp_tx_maint_s0 (r/w) tx_j0_ins 4 01378 j0 provisioned message buffer ohp_tx_j0byte0_s0 ohp_tx_j0byte31_s0 (r/w) tx_j0_exp_0 tx_j0_exp_31 4 01900 0191f
154 154 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 31 transmit transport overhead (toh) processor (continued) 31.1 functional description of toh processor (continued) 31.1.1.8 local orderwire (e1) the local orderwire byte is located only in the first sts-1 of the sts-48 or sts-192, and provides a 64 khz chan- nel for voice communications between regenerators, hubs, and remote terminals. if (tx_toac_enb) e1 = toac_controlled_data; else if (ohp_tx_soh_proc_dis) and not (tx_hw_insert_ais) e1 = received_system_data; else e1 = default_sonet_sdh; end 31.1.1.9 section user channel (f1) the section user channel byte is located only in the first sts-1 of the sts-48 or sts-192 and provides a 64 khz channel for use by the network provider. the byte is inserted in each frame using either a value provisioned in the f1 byte control register or from a value received on the toac data input. if (tx_toac_enb) f1 = toac_controlled_data; else if (tx_f1_ins) f1 = mpu_programmed_f1; else if (ohp_tx_soh_proc_dis) and not (tx_hw_insert_ais) f1 = received_system_data; else f1 = default_sonet_sdh; end table 127. transmit f1 register summary function register name (first occurrence) register bits qty. 1st addr (hex) byte insert control ohp_tx_maint_s0 (r/w) tx_f1_ins 4 01378 provisioned f1 byte ohp_tx_f1s1byte_s0 (r/w) tx_f1_byte 4 01388
agere systems inc. 155 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 31 transmit transport overhead (toh) processor (continued) 31.1 functional description of toh processor (continued) 31.1.1.10 section data communications channel (d1, d2, and d3) the section data communications channel bytes are located only in the first sts-1 of the sts-48 or sts-192, and are used as one 192 khz message-based channel for operations, administration, and maintenance (oa & m) com- munication. if (tx_toac_enb) d1_to_d3 = toac_controlled_data; else if (ohp_tx_soh_proc_dis) and not (tx_hw_insert_ais) d1_to_d3 = received_system_data; else d1_to_d3 = default_sonet_sdh; end 31.1.1.11 line bip-8 (b2) the line bip-8 b2 byte is provided in all the sts-1s of the sts-48 or sts-192. the computed b2 is inserted in these locations. if b2 calculation and toac insertion are enabled, the computed b2 value is xored with the received toac b2 byte value (if toac data enable is asserted on the msb of b2 byte). optionally, b2 can be cor- rupted by enabling the b2 corrupt enable bit. if (tx_line_ais_ins) or (tx_hw_insert_ais) b2 = 0xff; else if (toac mode) if (toac enable mode is 11) b2 = computed_b2 xor toac_data; else b2 = bypass, default, or software controlled depending on toac enable mode 01, 00, or 10; end if else if (ohp_tx_b2_bypass) b2 = received_system_data; else b2 = computed_b2; end
156 156 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 31 transmit transport overhead (toh) processor (continued) 31.1 functional description of toh processor (continued) 31.1.1.12 sts payload pointer (h1/h2/h3) the sts payload pointer bytes are normally set to the values received at the system interface. these values are overwritten under the following conditions (in order of precedence from highest to lowest): if the h1, h2, or h3 pointers are changed, then no other overhead processing is done. toac or software controls are ignored. software/hardware ais insertion: if enabled, overwrites the pointer bytes for the channel with 0xffffff. unequipped signal insertion: if enabled, overwrites the pointer bytes for the channel with 0x600000. prbs payload insertion: if enabled, overwrites the pointer bytes for the channel with 0x620a00. invalid pointer insertion: if enabled, overwrites the pointer bytes for the channel with 0x633300. ndf pointer insertion: if enabled, overwrites the pointer bytes for the channel with 0x920a00. toac data insertion: controlled by toac. if (tx_line_ais_ins) or (tx_hw_insert_ais) h1 = 0xff; h2 = 0xff; h3 = 0xff; else if (tx_line_uneq_ins) h1 = 0x60; h2 = 0x00; h3 = 0x00; else if (tx_prbs_enb) h1 = 0x62; h2 = 0x0a; h3 = 0x00; else if (tx_inv_ptr_ins) h1 = 0x63; h2 = 0x33; h3 = 0x00; else if (tx_ndf_ins) h1 = 0x92; h2 = 0x0a; h3 = 0x00; else if (tx_toac_enb) if (tx_line_ais_ins or tx_hw_insert_ais) h1 = non toac functionality h2 = non toac functionality h3 = non toac functionality else h1 = toac_controlled_data; h2 = toac_controlled_data; h3 = toac_controlled_data; else h1 = received_system_data; h2 = received_system_data; h3 = received_system_data; end
agere systems inc. 157 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 31 transmit transport overhead (toh) processor (continued) 31.1 functional description of toh processor (continued) table 128. transmit sts payload pointer register summary 31.1.1.13 aps channel (k1 and k2) the aps channel bytes are located only in the first sts-1 of the sts-48 or sts-192 and are used for automatic protection switching (aps) signaling to coordinate line level protection switching. in addition, the k2 byte is also used to carry line ais and line rdi signals. both bytes are inserted during each frame, normally using values stored in the k-byte register. in addition, the value of bits 2?0 in k2 can optionally be automatically overwritten by 110 (rdi-l) when ais-l, los, sef, or lof (sef and lof only if ais insertion is enabled) are detected for the receive sts-48 or sts-192. this insertion is controlled by the rdi-l select bit in the lte transmit channel mainte- nance register. when rdi-l is triggered, it will be inserted for a minimum of 20 consecutive frames, if not software disabled. if (tx_line_ais_ins) or (tx_hw_insert_ais) k1 = 0xff; k2 = 0xff; else if (tx_toac_enb) k1 = toac_controlled_data; if (tx_rdi_l_sel) and (tx_hw_insert_rdi) k2 = k2[7:3] & ?110?; else if (tx_rdi_l_sel) k2 = toac_controlled_data; end else if (aps_bypass) k1 = by pass data; k2 = by pass data; else k1 = mpu_programmed_k1; if (tx_rdi_l_sel) and (tx_hw_insert_rdi) k2 = k2[7:3] & ?110?; else if (tx_rdi_l_sel) k2 = toac_controlled_data; end end function register name (first occurrence) register bits qty. 1st addr (hex) ndf insert control ohp_tx_maint_s0 (r/w) tx_ndf_ins 4 01378 invalid pointer insert control tx_inv_ptr_ins 4 01378 uneq-l insert control tx_line_uneq_ins 4 01378
158 158 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 31 transmit transport overhead (toh) processor (continued) 31.1 functional description of toh processor (continued) table 129. transmit aps channel (k1k2) register summary 31.1.1.14 line data communication channel (d4?d12) the line data communications channel bytes are located only in the first sts-1 of the sts-48 or sts-192, and are used as one 576 khz message-based channel for operations, administration, and maintenance communication. if (tx_line_ais_ins) or (tx_hw_insert_ais) d4_to_d12 = 0xff; else if (tx_toac_enb) d4_to_d12 = toac_controlled_data; else if (ohp_tx_loh_proc_dis) d4_to_d12 = received_system_data; else d4_to_d12 = default_sonet_sdh; end 31.1.1.15 synchronization status (s1) the synchronization status byte is located only in the first sts-1 of the sts-48 or sts-192 and is used to convey the synchronization status of a network element. the byte is inserted in each frame using either a value provi- sioned in the s1 byte control register or from a value received on the toac data input. if (tx_line_ais_ins) or (tx_hw_insert_ais) s1 = 0xff; else if (tx_toac_enb) s1 = toac_controlled_data; else if (tx_s1_ins) s1 = mpu_programmed_s1; else if (ohp_tx_loh_proc_dis) s1 = received_system_data; else s1 = default_sonet_sdh; end table 130. transmit synchronization status (s1) register summary function register name (first occurrence) register bits qty. 1st addr (hex) k1k2 software insert control ohp_tx_maint_s0 (r/w) tx_k1k2_bypass 4 01378 k1k2 software insert value ohp_tx_k1k2byte_s0 (r/w) tx_k1_byte tx_k2_byte 40138c rdi-l duration control ohp_tx_ais_rdi_s0 (r/w) tx_20frm_rdi_dis 4 01374 rdi-l insert control ohp_tx_maint_s0 (r/w) tx_rdi_l_sel 4 01378 function register name (first occurrence) register bits qty. 1st addr (hex) byte insert control ohp_tx_maint_s0 (r/w) tx_s1_ins 4 01378 provisioned s1 byte ohp_tx_f1s1byte_s0 (r/w) tx_s1_byte 4 01388
agere systems inc. 159 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 31 transmit transport overhead (toh) processor (continued) 31.1 functional description of toh processor (continued) 31.1.1.16 sts-192 line remote error indication (m1) the line remote error indication (rei-l) byte is located only in the third sts-1 of the sts-48 or sts-192 (in order of appearance in the sts-192 signal) and is used to convey to the far end the number of errors detected in the receive direction using the line bip-8 bytes. the byte is inserted each frame with a binary value indicating the num- ber of line bip-8 errors (truncated at 255) detected in the previous receive frame for the entire sts-48 or sts-192. the value of the byte can be fully corrupted (by setting all bits) on a per sts-48 channel basis using the m1 corrupt enable control bit. the duration of the corruption is defined in frames per second, up to a maximum of 8000 frames (1 second), and corruption starts with the next frame after the rising edge of performance monitoring clock. the m1 corrupt frame count register specifies this duration. if (tx_line_ais_ins) or (tx_hw_insert_ais) m1 = 0xff; else if (tx_toac_enb) m1 = toac_controlled_data; else if (tx_m1corrupt_en) m1 = 0xff; else if (tx_m1_ins) m1 = monitored_b2_error_count; else if (ohp_tx_loh_proc_dis) m1 = received_system_data; else m1 = 0x00; end table 131. transmit m1 register summary 31.1.1.17 express orderwire (e2) the express orderwire byte is located only in the first sts-1 of the sts-48 or sts-192 and provides a 64 khz channel for voice communications between line entities. if (tx_line_ais_ins) or (tx_hw_insert_ais) e2 = 0xff; else if (tx_toac_enb) e2 = toac_controlled_data; else if (ohp_tx_loh_proc_dis) e2 = received_system_data; else e2 = default_sonet_sdh; end function register name (first occurrence) register bits qty. 1st addr (hex) byte insert control ohp_tx_maint_s0 (r/w) tx_m1_ins 4 01378 m1 corrupt enable ohp_tx_prov_s0 (r/w) tx_m1corrupt_enb 4 01370 m1 corrupt duration control ohp_tx_m1corrupt_s0 (r/w) tx_m1corrupt_frm_cnt 4 01384
160 160 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 32 receive toac drop/transmit toac insert four toac insert/drop functions are provided in quad sts-48/stm-16 mode and one in sts-192/stm-64 mode. 32.1 receive toac drop in the receive direction (toac drop), each transport overhead byte is extracted in each frame, buffered, and output msn (most significant nibble) first (4 bits on 4 pins), with each bit output on the positive edge of the toac clock (20.736 mhz (full)/1.728 mhz (partial)). during ais insertion, due to los, lof, or sef (provisionable), 0xff is constantly output. the location of the msn of the first a1 byte is identified by the toac sync output going high. in sts-48 mode, each of the four toac data pins per sts-48 frame transmits the transport overhead for an sts-48 channel. in sts-192 mode, four sets of four toac data pins transmit the entire sts-192 overhead (5184 bytes), where the fourth set of four toac data pins transmit sts channels 1 through 48, the third set of four toac data pins transmit sts channels 49 through 96, the second set of four toac data pins transmit channels 97 through 144, and the first set of four toac data pins transmit channels 145 through 192. internally, a memory is used for each channel in order to buffer the data and transfer it between the internal pro- cessing rate and the external data rate. this allows for the data to be transmitted in a nongapped manner. the operation of the memory is monitored using parity and any errors are reported using the toac data parity error alarm bit. this alarm bit is present in the corresponding lte receive channel nonservice-affecting interrupt alarm register and is valid regardless of the mode (sts-48/stm-16 or sts-192/stm-48) of the device. 32.2 transmit toac insert in the transmit direction (toac insert), each transport overhead byte for each sts-48 (individual or part of an sts-192) can be sourced serially using the four toac data pins allocated per sts-48 channel. insertion of these received bytes is controlled through a global toac insert enable bit in the transmit provisioning register. the inser- tion is then enabled on a per-byte basis by strobing the toac data enable pin high during the entire period of the byte to insert. the bytes are received msn (most significant nibble) first (4 bits on 4 pins), with each bit output on the positive edge of the toac clock (20.736 mhz (full)/1.728 mhz (partial)). the location of the msn (most signifi- cant nibble) bit of the first a1 byte is identified by the toac sync output going high. for b2, the value received is actually used as an xor corruption mask for the internally calculated values. in sts-48 mode, the individual toac data pins, along with the toac enable pin, capture the transport overhead for that sts-48 channel. in sts-192 mode, the four sets of four toac data pins, along with their respective toac enable pins, capture the entire sts-192 overhead (5184 bytes), where the fourth set of four toac data pins cap- ture sts channels 1 through 48, the third set of four toac data pins capture sts channels 49 through 96, the second set of four toac data pins capture channels 97 through 144, and the first set of four toac data pins cap- ture channels 145 through 192. internally, a memory is used for each channel to buffer the data and transfer it between the external data rate and the internal data rate. the operation of the memory is monitored using parity and any errors are reported using the toac data parity error alarm bit. this alarm bit is present in the lte transmit interrupt alarm register and is valid regardless of the mode (sts-48 or sts-192) in which the device is operating. when enabled, the overhead serial link takes precedence over all other overhead sources, with the exception of bytes that are software enabled.
agere systems inc. 161 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 32 transmit transport overhead (toh) processor (continued) 32.3 toac modes both the receive toac drop and transmit toac insert interfaces can operate in two modes: full toac insert/drop mode and partial insert/drop mode (see section 32.3.1 and section 32.3.2 on page 161). 32.3.1 full toac insert/drop mode toac clock output at 20.736 mhz. toac sync output 8 khz coincide with the msn (most significant nibble) of the first a1 nibble. toac data enable input (tx only) active during the msn (most significant nibble) of each byte to be inserted into the output stream. toac data bus (transmit insert input/receive drop output): ? in sts-48 mode, four bits/stream at 20.736 mbits/s that transition at the rising edge of the clock (10,368 bits per sts-48/stm-16 sonet/sdh frame). ? in sts-192 mode, sixteen bits at 20.736 mbits/s that transition at the rising edge of the clock ([10368 4] = 41472 bits per sts-192/stm-64 sonet/sdh frame). the byte ordering of the individual sts-1s or sts-1 components of an sts-nc that comprise the sts-192 and the details of the sts-192 to sts-48 demultiplexing can be found in gr-253-core section 5-1, network element architectural features (multiplexing procedure) , page 5-1. the toac channels output/accept the nibble data in sts-48/stm-16 byte ordering independent of the full drop/insert mode. therefore, in sts-192/stm-64 mode, four toac channels are needed to drop/insert the entire transport overhead bytes. a byte is inserted into the transmit data stream through an external input that is sampled per clock cycle. if the signal is active (high) during the msb/ msn (most significant bit/nibble), the byte is inserted into the transmitted overhead stream. 32.3.2 partial toac insert/drop mode first sts-1/stm-0 (j0, e1, d1?d3, d4?d12, s1, e2, including the m1 byte accessible): toac clock output at 1.728 mhz (in 10 gbits/s mode, only rtoac_clko_4, rtoac_synco_4, and rtoac_datao_4 are used). toac sync output at 8 khz coincide with the msn (most significant nibble) of the first a1 nibble. toac data enable input (tx only) active during the msn (most significant nibble) of each byte to be inserted into the output stream. toac data bus (transmit insert input/receive drop output): ? one bit/stream at 1.728 mbits/s that transitions at the rising edge of the clock (216 bits per sts-192/stm-64 or sts-48/stm-16 frame).
162 162 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 32 receive toac drop/transmit toac insert (continued) 32.3 toac modes (continued) table 132 summarizes the frame format in the sts-1/stm-0 mode. data is transmitted from left to right, then top to bottom with a1 bit 7 being the first bit to be transmitted/received. table 133. receive overhead serial links register summary table 134. transmit overhead serial links register summary 33 receive/transmit payload processing 33.1 receive payload processing in the receive direction, optionally, the payload data of an sts-192c/sts-48c can be monitored with a prbs ana- lyzer. this prbs monitor is provided per sts-48 for continuity checking. the pointer value of the receive sts-48c signal must be 522 1 . this allows monitoring without the need for a pointer interpreter. three different prbs moni- toring sequences are supported: prbs15, prbs20, and prbs23. additionally, each of the prbs data received can be programmed to be inverted before monitoring. monitoring can be done in two modes. in full spe monitor- ing, the complete payload as well as poh bytes contains prbs data. in normal spe monitoring, only the payload bytes contain the prbs data; poh bytes and stuff bytes are ignored. table 132. toac insert/drop frame format?sts-1/stm-0 mode row column numbers 123 section/rs 1a1a2j0 2b1e1f1 3 d1d2d3 line/ms 4 h1h2h3 5 b2k1k2 6 d4d5d6 7 d7d8d9 8 d10 d11 d12 9s1m1 1 1. the z2 byte is overwritten by the m1 value. e2 function register name (first occurrence) register bits qty. 1st addr (hex) toac byte drop control ohp_rx_prov_s0 (r/w) rx_toac_mode 4 01310 function register name (first occurrence) register bits qty. 1st addr (hex) global toac byte insert control ohp_tx_prov_s0 (r/w) tx_toac_enb tx_toac_mode 4 01370 1. the pointer is set by the incoming signal. only when prbs data is injected into the sonet frame is the pointer set, by the de vice, to 522.
agere systems inc. 163 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 33 receive/transmit payload processing (continued) 33.1 receive payload processing (continued) table 135. receive prbs payload type table 136. receive prbs register summary 33.2 transmit payload processing in the transmit direction, optionally, internally generated prbs data can be inserted as the sts-192c/sts-48c payload. this prbs generator is provided per sts-48 for continuity checking. four sts-48 prbs signals are inserted in an sts-192 signal for 10 gbits/s mode. the prbs generated signal is placed in the sts-192c/sts-48c payload with a fixed pointer value of 522 1 . three different prbs generation sequences are supported: prbs15, prbs20, and prbs23. additionally, each of the prbs data transmitted can be programmed to be inverted before monitoring. insertion can be done in two modes. in full spe insertion, the complete payload as well as poh bytes contains prbs data. in normal spe insertion, only the payload bytes contain the prbs data; poh bytes and the sts-48c/sts-192c stuff bytes are ignored. table 137. transmit prbs payload type register bits value description rx_prbs_type 01 prbs15 10 prbs20 00, 11 prbs23 function register name (first occurrence) register bits qty. 1st addr (hex) prbs out-of-sync alarm ohp_rx_nsa_0_alarm_s0 (w1c) rx_prbs_oos_a 4 0102c prbs out-of-sync alarm mask ohp_rx_nsa_0_mask_s0 (r/w) rx_prbs_oos_m 4 01078 prbs out-of-sync state ohp_rx_nsa_0_state_s0 (ro) rx_prbs_oos 4 010ec prbs out-of-sync persistency ohp_rx_nsa_0_persist_s0 (ro) rx_prbs_oos_p 4 010bc prbs data inversion enable ohp_rx_prov_s0 (r/w) rx_prbs_inv 4 01310 prbs data type ohp_rx_prov_s0 (r/w) rx_prbs_type 4 01310 prbs mode ohp_rx_prov_s0 (r/w) rx_prbs_mode 4 01310 prbs data monitoring enable ohp_rx_prov_s0 (r/w) rx_prbs_enb 4 01310 prbs ber count ohp_rx_prbs_ber_s0 (cor) rx_prbs_ber_cnt0 4 01600 1. the pointer is set by the incoming signal. only when prbs data is injected into the sonet frame is the pointer set, by the de vice, to 522. register bits value description tx_prbs_type 01 prbs15 10 prbs20 00, 11 prbs23
164 164 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 33 receive/transmit payload processing (continued) 33.2 transmit payload processing (continued) table 138. transmit prbs register summary 34 b2 computing 34.1 functional description of b2 computing the line bip-8 is located in each sts-1 of the sts-48 or sts-192 and carries the even parity for the line overhead and spe data in the previous sts-1 frame. since the b2 byte is calculated for each sts-1 independent of the other sts-1s, the device mode (sts-48 or sts-192) does not affect the operation of this block. the b2 values in all sts-1s in an sts-48 channel can be fully corrupted (by inverting all the bits) on a per sts-48 basis, using the b2 corrupt enable control bit. the duration of the corruption is defined in frames per second, up to a maximum of 8000 frames (1 second) between rising edges of the performance monitoring clock. the b2 corrupt frame count register specifies this duration. table 139. b2 register summary function register name (first occurrence) register bits qty. 1st addr (hex) prbs data inversion enable ohp_tx_prov_s0 (r/w) tx_prbs_inv 4 01370 prbs data type tx_prbs_type 4 01370 prbs mode tx_prbs_mode 4 01370 prbs data insertion enable tx_prbs_enb 4 01370 function register name (first occurrence) register bits qty. 1st addr (hex) b2 calculation disable sonfec_rx_bypass_s0 (r/w) ohp_rx_b2cal_dis 4 01115 b2 corrupt enable ohp_rx_prov_s0 (r/w) rx_b2corrupt_enb 4 01310 b2 corrupt duration control ohp_rx_b2corrupt_s0 (r/w) rx_b2corrupt_frm_cnt 4 01320
agere systems inc. 165 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 35 transpose multiplexer (tmx) 35.1 functional description of the tmx in sts-192 mode, the bytes in the four sts-48 channels need to be combined and reordered to create an sts-192 data stream. this is performed by the transpose multiplexer (tmx). the byte ordering of the individual sts-1s, or sts-1 components of an sts-nc, that comprise the sts-48 as it enters the tdmx and after the tdmx (sts-192 byte ordering) and the details of the sts-48 to sts-192 multiplexing can be found in gr-253-core section 5-1, network element architectural features (multiplexing procedure) , page 5-1. if the device is in sts-48 mode, the data is received on all four channels and the tmx is bypassed. the module receives individual sts-48 bytes every clock period from each sts-48 and will output 16 bytes on the sts-192. because sonet interleaving causes each sts-48 bandwidth to be multiplexed into an sts-192 16 bytes at a time, each sts-48 must have 16 bytes stored and then output every fourth clock on the 16-byte wide sts-192 output. that is, each sts-48 must source all 16 bytes in the sts-192 word once every four clocks. table 140. transpose multiplexer register summary 36 scrambler 36.1 functional description of the scrambler in the transpose multiplexer the data stream is optionally scrambled using the standard generator polynomial 1 + x 6 +x 7 . the scrambling can be disabled by the corresponding scrambler disable bit of the lte channel n provisioning register. table 141. scrambler register summary function register name (first occurrence) register bits qty. 1st addr (hex) transpose multiplexer disable control sonfec_rx_tp_bypass (r/w) rx_tmx_dis 1 01112 function register name (first occurrence) register bits qty. 1st addr (hex) scrambler disable control sonfec_rx_bypass_s0 (r/w) ohp_rx_scrm_dis 4 01115 scrambler mode control sonfec_rx_mode (r/w) rx_scr_mode 1 01110
166 166 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 37 b1 computing 37.1 functional description of b1 computing the section bip-8 byte is located only in the first sts-1 of the sts-48 or sts-192 and carries the even parity of the scrambled data in the previous sts-192 frame. in every frame, the calculated bip-8 for the previous frame is inserted in the b1 byte of the current frame prior to scrambling. the b1 value can be fully corrupted (by inverting all bits) on a per-channel basis using the b1 corrupt enable control bit. the duration of the corruption is defined in frames per second, up to a maximum of 8000 frames (1 second) between rising edges of performance monitoring clock. the b1 corrupt frame count register specifies this duration. table 142. b1 computing register summary function register name (first occurrence) register bits qty. 1st addr (hex) b1 calculation disable sonfec_rx_bypass_s0 (r/w) ohp_rx_b1cal_dis 4 01115 b1 calculation mode sonfec_rx_mode (r/w) rx_b1calc_mode 1 01110 b1 corrupt enable ohp_rx_prov_s0 (r/w) rx_b1corrupt_enb 4 01310 b1 corrupt duration control ohp_rx_b1corrupt_s0 (r/w) rx_b1corrupt_frm_cnt 4 0131c
agere systems inc. 167 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 38 microprocessor interface 38.1 microprocessor interface overview the tfec0410g microprocessor interface architecture is configured for glueless interface to the motorola mpc860 and mc68360 microprocessors. the intel microcontrollers 8xc251 and 80c196 and the i960 micropro- cessor may also be utilized to interface to the tfec0410g. however, provisions on the board need to be made to (de)multiplex the address and data bus. the state of the mptype_im input signal indicates to the device whether it interfaces to a motorola microprocessor or an intel microcontroller. other microprocessors may be used if their timing requirements fit to one of the modes described. the tfec0410g has separate 16-bit wide address and data buses. the mpdb_8_16 input distinguishes between an 8-bit or 16-bit wide microprocessor data bus being used. in case of an 8-bit wide microprocessor data bus inter- face, the eight upper bits of the device data bus ports are not being used and are held 3-state. the microprocessor interface operates at the frequency of the microprocessor clock (pclk) input, which should be in the range of 10 mhz to 100 mhz. depending on the state of the mpmode_as input signal, the interface to the 80960sx microprocessor is synchro- nous, while the interface to the 8xc251 and 80c196 microcontrollers is asynchronous. similarly, with the mpc860 or mc68360 microprocessors being used, the state of the mpmode_as input signal determines whether bus transfers are synchronous or asynchronous, respectively. in this case, the microprocessor interface also generates an external processor bus error if an internal data acknowledgment is not received in a predetermined period of time, or on parity errors if the mpparen input is enabled. all internal counters are latched using an external or internal performance monitor (pm) latch pulse that must occur once per second to ensure all internal counters do not saturate. persistency alarm registers are used in conjunction with the interrupt alarm registers to indicate whether alarms are persistent. the tfec0410g contains 48 general purpose inputs/outputs (gpios), which can be used to monitor signals on the board. 38.2 subblock address space assignment the 16-bit address space is assigned to the subblocks of the device, as shown in table 143. table 143. subblock address space assignment base address block block name 0x0000 microprocessor interface/top level. mpu 0x1000 dwfec macro. dwfec 0x2000 sonfec macro. sonfec 0x3000 unused. ?
168 168 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 38 microprocessor interface (continued) 38.2 microprocessor interface overview (continued) table 144. mpu general register summary 38.3 microprocessor interface modes table 145 highlights the four microprocessor modes controlled by the mptype_im and mpmode_as inputs. table 145. microprocessor configuration modes 38.4 microprocessor interface pinout descriptions the mode[1?4] specific pin definitions are given in table 146. note that the microprocessor interface uses the same set of pins in all modes. function register name (first occurrence) register bits qty. 1st addr (hex) version control dev_ver (ro) dev_ver 1 00 device identification 0 dev_id0 (ro) dev_id0 1 01 device identification 1 dev_id1 (ro) dev_id1 1 02 device identification 2 dev_id2 (ro) dev_id2 1 03 device identification 3 dev_id3 (ro) dev_id3 1 04 device identification 4 dev_id4 (ro) dev_id4 1 05 scratch dev_scratch (r/w) dev_scratch 1 0200 mode mptype_im mpmode_as description typical application mode 1 1 1 synchronous interface; handshake using data acknowledge. mpc860 mode 2 1 0 asynchronous interface; handshake using data acknowledge. mc68360, mc68hc16x mode 3 0 1 synchronous interface; handshake through inserted wait states; asynchronous address latching. i960 (80960sx) mode 4 0 0 asynchronous interface; handshake through inserted wait states; asynchronous address latching. 80c196, 8xc251
agere systems inc. 169 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 38 microprocessor interface (continued) 38.4 microprocessor interface pinout descriptions (continued) table 146. mode[1?4] microprocessor pin definitions configuration device pin name microprocessor pin name pin type assertion sense function mode 1 cs_n cs input active-low chip select. ts_n ts input active-low transfer start. rw_n r/w input ? read/write: rw_n = 1 for read. rw_n = 0 for write. address a input ? address bus. data d i/o ? data bus. parity dp i/o ? parity bus (odd parity supported only). ta_n ta output active-low transfer acknowledge. tea_n tea output active-low transfer error acknowledge. inth_n/ intl_n irq* output active-low interrupt. mode 2 cs_n cs input active-low chip select. ts_n ts input active-low transfer start. rw_n r/w input ? read/write: rw_n = 1 for read. rw_n = 0 for write. ds_n ds +input active-low data strobe. address a input ? address bus. data d i/o ? data bus. parity prty i/o ? parity bus. ta_n dsack* output active-low transfer acknowledge. tea_n berr output active-low bus error. inth_n/ intl_n irq* output active-low interrupt. mode 3 cs_n ? input active-low chip select. ts_n ale input active-high address latch enable. rw_n w/r input ? write/read: rw_n = 0 for read. rw_n = 1 for write. ds_n as input active-low address strobe. address ad input ? address bus. data ad i/o ? data bus. ta_n ready output active-low ready signal. inth_n/ intl_n int* output active-low interrupt.
170 170 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 38.5 reset behavior the microprocessor interface can be reset by driving the pin rst_n active-low. it will take about 5 clock cycles of pclk after the reset gets negated until the microprocessor interface is fully functional. the software reset registers (0300?0304) can be used to reset parts of the device. those registers themselves can only be reset by the hardware reset, i.e., by pulling rst_n active low. after a reset of the mpu macro, the mpu registers within the sonfec and dwfec macro are powered down and held in reset. they can be put back to function by enabling the bits dev_sonfec_pclk_pdn and dev_dwfec_pclk_pdn in the dev_pdn_iclk register. note that all previously programmed values in the mpu registers of sonfec and dwfec will be lost during powerdown. similarly, the clock muxing control register dev_ctl_clkmux[0:4]_s[0:3] will disable the internal functional clocks upon a reset of the mpu macro. all registers that rely on a functional clock to write or return data will not be accessible before those clocks are enabled. this affects the prbs counter registers ohp_rx_prbs_ber_s[0:3] in the sonfec macro and dw_rx_cnt_prbs_s[0:3] in the dwfec macro. an attempt to access those regis- ters in this case will cause the microprocessor interface to get stuck waiting for an internal acknowledge. in mode 1 and mode 2, the interface will time-out itself and generate a processor bus error (see section 38.7, trans- fer error acknowledge (mode 1 and mode 2 only), on page 171). in mode 3 and mode 4, the microprocessor inter- face can be reset from this state by negating and asserting cs_n. in general, the microprocessor interface will terminate any access after detecting cs_n being negated. mode 4 cs_n csx input active-low chip select. ts_n ale input active-high address latch enable. rw_n rd input active-low read enable. ds_n wr input active-low write enable. address ad input ? address bus. data ad, d i/o ? data bus. ta_n ready , wait output active-low ready, wait signal. inth_n/ intl_n int* output active-low interrupt. 38 microprocessor interface (continued) 38.4 microprocessor interface pinout descriptions (continued) table 146. mode[1?4] microprocessor pin definitions (continued) configuration device pin name microprocessor pin name pin type assertion sense function
agere systems inc. 171 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 38 microprocessor interface (continued) 38.6 microprocessor data bus width the microprocessor allows the connection of either an 8-bit or 16-bit wide data bus. the mpdb_8_16 input signal indicates which data bus width is being used. mpdb_8_16 = 0 assumes 8-bit data bus transfers, while mpdb_8_16 = 1 assumes 16-bit data bus transfers. the mpdb_8_16 input is supposed to be a static input. since all internal registers of the tfec0410g are 16 bits wide, an additional holding register is needed to facilitate an 8-bit data transfer. this implies that on an 8-bit data bus, two accesses are necessary to read or write the com- plete contents of an internal register. the internal holding register is 8 bits wide and resides at the address location 0x500. it is connected to the upper byte of the internal data bus that connects to the registers. to write an internal register, a first access needs to write the upper byte of the 16-bit data to the holding register. during a second write, the lower byte of the data together with the contents of the holding register gets written to the address location specified. similarly, in read mode, the upper byte of the register that was specified by the address gets loaded in the holding register, while the lower byte is visible on the external data bus. during a second read access, the upper byte can be made available on the data bus by reading the holding register. table 147. hold register summary 38.7 transfer error acknowledge (mode 1 and mode 2 only) the tfec0410g contains a bus time-out counter. it will terminate the device access if an internal data acknowl- edgment is not received within 32 pclk periods, in case of an access to an undefined address region. this interval is used since all valid internal accesses to the device will be completed in significantly less than 32 pclk periods. the transfer error acknowledge output tea_n will be driven low in the event of a bus time-out. this feature must be considered with respect to the external processor?s ability to generate its own bus time-out. the output pin tea_n is asserted in conjunction with ta_n, if the calculated parity value does not match the parity generated by the external microprocessor on a data transfer and the input mpparen is driven high. the device only supports odd parity. function register name (first occurrence) register bits qty. 1st addr (hex) 8-bit mode hold register dev_hold (r/w) dev_hold 1 0500
172 172 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 38 microprocessor interface (continued) 38.8 interrupt structure the interrupt structure of the tfec0410g is designed to minimize the effort for software/firmware to isolate the interrupt source. the interrupt structure is comprised of different registers, depending on the consolidation level. at the lowest level (source level), there are the three following registers: alarm register (ar), typically of the write-1-clear (w1c) type. interrupt mask (im) register of the read/write (r/w) type. persistency alarm (pa) register of the read-only (ro) type. an alarm register latches a raw status alarm. this latched alarm may contribute to an interrupt if its corresponding interrupt mask bit is enabled. individual latched alarms are consolidated into an interrupt status register (isr). if any of the latched alarms that are consolidated into a bit of an isr are set and unmasked, the isr bit is set. the isr bit may contribute to an interrupt if its corresponding interrupt mask bit is disabled. isrs may be consolidated into a higher-level isr in a similar fashion until all alarms are consolidated into the chip-level isr. the alarm regis- ter that causes an interrupt can be determined by traversing the tree of isrs, starting at the chip-level isr, until the source alarm is found. the raw nonregistered interrupt source can also be accessed through an address in the address map where applicable. at the chip level, all high-priority interrupts, e.g., loc, are grouped together into one isr and all lower-level inter- rupts, e.g., bit error, etc., are grouped into another isr. there will be two dedicated device outputs, one for high- priority interrupts and one for low-priority interrupts. in the case that the microprocessor supports only one interrupt input, the low-priority isr can be mapped into one maskable bit of the high-priority isr and will be observable on that output pin. note: interrupts are masked when the corresponding bit in the mask register is 0. if the mask register bit is 1, the interrupt is enabled. 38.9 interrupt alarm and interrupt persistency registers an alarm is persistent if it has been asserted continuously (i.e., the alarm has not been negated from the time it was asserted to the time it was read by software). an alarm is not persistent if it is negated one or more times from the point at which it was asserted to the point at which it was read by software. the persistency register monitors the state of an alarm point, and indicates to software whether the alarm is persis- tent. the following timing diagram (figure 54) indicates the operation of the persistency register relative to the raw status alarm, and its corresponding interrupt alarm register. it also describes the software interaction with respect to its attempt to clear the alarm and its interpretation. at the rising edge of the raw alarm point, the corresponding interrupt alarm and persistency alarm register are set. the falling edge of the raw alarm causes the persistency alarm register to be reset (cleared). any subsequent assertion of the raw alarm does not cause the persistency alarm register to be asserted. it remains reset until the interrupt alarm register is cleared (after the raw alarm is negated and the interrupt alarm register is cleared). once the interrupt alarm register is cleared, its corresponding persistency alarm register reset is released. the persis- tency register is now able to be set on the next assertion of the raw alarm point. note: for the raw alarm to be reliably latched by pclk, it needs to be stable for at least 10 clock cycles of a 78 mhz/83 mhz internal clock.
agere systems inc. 173 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 38 microprocessor interface (continued) 38.9 interrupt alarm and interrupt persistency registers (continued) note: all above registers can be read at any time by software to have the interrupt status evaluated without any impact to their state. figure 54. persistency register operation 38.10 performance monitor (pm) clock the pm_clk signal is sent to all blocks for performance monitoring (collecting statistics). pm_clk can come from an external pin, an internal 1 s timer, or be controlled by software, depending on the pm mode dev_pmmode[1:0] bits. the external pm_clk pin is a bidirectional signal controlled by the dev_pmclk_ioctl bit. this bit defaults to 0, making the pin an input. table 148. pmclk configuration and interrupt register summary function register name (first occurrence) register bits qty. 1st addr (hex) pmclk configuration dev_pmclk_cfg (r/w) dev_pmmode 1 0100 pmclk configuration dev_pmclk_cfg (r/w) dev_pmclk_ioctl 1 0100 pm counter preload value dev_pmclk_preld (r/w) dev_pmclk_preld 1 0101 software reset for mpu registers dev_mpureg_swrst (r/w) dev_pm_trig_swrst 1 0300 pmclk interrupt alarm dev_pmclk_alarm (w1c) dev_pmclk_a 1 01b pmclk interrupt alarm mask dev_pmclk_mask (r/w) dev_pmclk_m 1 04a raw alarm/alarm state (ro) interrupt alarm register (r/w1c) persistency register (ro) software clears interrupt persistency register is now released to be set again. alarm register after write; software attempts to clear since raw alarm is active, nothing happens. interrupt alarm register; raw alarm event interrupt alarm and persistency gets latched into register. raw alarm which clears persistency gets inactive register. raw alarm becomes that raw alarm was not was set. active again; persistency register stays cleared persistent since interrupt alarm register to indicate to software
174 174 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 38 microprocessor interface (continued) 38.10 performance monitor (pm) clock (continued) table 149. pmclk counter register summary 38.11 general purpose input/output (gpio) the programmable i/o general purpose input/output (gpio) consists of 48 device pins that can be used for internal or external signal observation. these pins can be configured to be either inputs or outputs, depending on the dev_gpio_cfg[47:0] bits. these pins are useful for board designers who need the ability to monitor or control signals on their boards. if a gpio pin is configured for input, it can be programmed to generate either a level-sensitive interrupt, a positive edge detect interrupt, a negative edge detect interrupt, or both edges detect interrupt contributing to the composite external interrupt. the raw value on this pin can be read from the dev_gpi_state[47:0] bits. the interrupt alarm register is dev_gpi_alarm and the corresponding mask and persistency registers are dev_gpi_mask and dev_gpi_persist, respectively. if a gpio pin is configured for output, different internal signals can be monitored depending on the four select bits for that pin in the dev_gpo_sel[0?3] registers. note that only the lower 16 gpio pins can be used to monitor internal signals, while the other gpio pins are connected to an internal register permanently. select bits = 0000: the value provisioned in the dev_gpo_val[47:0] bits will appear on the device pin immedi- ately. function register name qty. 1st addr (hex) receive performance monitoring register [4:0] ohp_rx_pm 4 0132c receive rei-l performance monitoring [20:16] ohp_rx_rei_u_pm 4 01338 receive rei-l performance monitoring [15:0] ohp_rx_rei_l_pm 4 01339 receive cv-l performance monitoring [23:16] ohp_rx_post_cvl_u_pm 4 01341 receive cv-l performance monitoring [15:0] ohp_rx_post_cvl_l_pm 4 01342 receive cv-l performance monitoring [23:16] ohp_rx_pre_cvl_u_pm 4 0134a receive cv-l performance monitoring [15:0] ohp_rx_pre_cvl_l_pm 4 0134b receive cv-s performance monitoring [15:0] ohp_rx_cvs_pm 4 01353 transmit pm register [4:0] ohp_tx_pm 4 01394 transmit cv-l performance monitoring [23:16] ohp_tx_cvl_u_pm 4 0139c transmit cv-l performance monitoring [15:0] ohp_tx_cvl_l_pm 4 0139d transmit cv-s performance monitoring [15:0] ohp_tx_cvs_pm 4 013a5 dw bip-0 counter [26:16] dw_rx_cnt_bip00 4 02328 dw bip-0 counter [15:0] dw_rx_cnt_bip01 4 02329 dw bip-1 counter [26:16] dw_rx_cnt_bip10 4 02331 dw bip-1 counter [15:0] dw_rx_cnt_bip11 4 02332 dw bei-0 counter [26:16] dw_rx_cnt_bei00 4 0233a dw bei-0 counter [15:0] dw_rx_cnt_bei01 4 0233b dw bei-1 counter [26:16] dw_rx_cnt_bei10 4 02343 dw bei-1 counter [15:0] dw_rx_cnt_bei11 4 02344
agere systems inc. 175 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 38 microprocessor interface (continued) 38.11 general purpose input/output (gpio) (continued) select bits = 0001: the value of an alarm status signal will be visible at the pin according to the assignment in table 150. note that pins 16?47 are undefined in this case. table 150. gpio pin assignment when select bits = 0001 select bits = 0010: the value of the transmit and receive phase detector reference and variable signals will be vis- ible at the pin according to the assignment in table 151. note that pins 16?47 are undefined in this case. table 151. gpio pin assignment when select bits = 0010 gpio pin internal signal 15 slice 3, sonfec tx composite alarm. 14 slice 2, sonfec tx composite alarm. 13 slice 1, sonfec tx composite alarm. 12 slice 0, sonfec tx composite alarm. 11 slice 3, dwfec tx composite alarm. 10 slice 2, dwfec tx composite alarm. 9 slice 1, dwfec tx composite alarm. 8 slice 0, dwfec tx composite alarms. 7 slice 3, sonfec rx composite alarm. 6 slice 2, sonfec rx composite alarm. 5 slice 1, sonfec rx composite alarm. 4 slice 0, sonfec rx composite alarm. 3 slice 3, dwfec rx composite alarm. 2 slice 2, dwfec rx composite alarm. 1 slice 1, dwfec rx composite alarm. 0 slice 0, dwfec rx composite alarms. gpio pin internal signal 15 slice 3?phase detector tx variable signal (44.434 mhz). 14 slice 2?phase detector tx variable signal (44.434 mhz). 13 slice 1?phase detector tx variable signal (44.434 mhz). 12 slice 0?phase detector tx variable signal (44.434 mhz). 11 slice 3?phase detector tx reference signal (44.434 mhz). 10 slice 2?phase detector tx reference signal (44.434 mhz). 9 slice 1?phase detector tx reference signal (44.434 mhz). 8 slice 0?phase detector tx reference signal (44.434 mhz). 7 slice 3?phase detector rx variable signal (44.434 mhz). 6 slice 2?phase detector rx variable signal (44.434 mhz). 5 slice 1?phase detector rx variable signal (44.434 mhz). 4 slice 0?phase detector rx variable signal (44.434 mhz). 3 slice 3?phase detector rx reference signal (44.434 mhz). 2 slice 2?phase detector rx reference signal (44.434 mhz). 1 slice 1?phase detector rx reference signal (44.434 mhz). 0 slice 0?phase detector rx reference signal (44.434 mhz).
176 176 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 38 microprocessor interface (continued) 38.11 general purpose input/output (gpio) (continued) select bits = 0011: the value of an alarm status signal will be visible at the pin according to the assignment in table 152. note that pins 16?47 are undefined in this case. table 152. gpio pin assignment when select bits = 0011 select bits = others: logic 0. gpio pin internal signal 15 logic 0. 14 logic 0. 13 logic 0. 12 logic 0. 11 logic 0. 10 logic 0. 9 logic 0. 8 logic 0. 7 slice 3?sonfec tx free-running 8 khz signal. 6 slice 2?sonfec tx free-running 8 khz signal. 5 slice 1?sonfec tx free-running 8 khz signal. 4 slice 0?sonfec tx free-running 8 khz signal. 3 slice 3?dwfec tx free-running 8 khz signal. 2 slice 2?dwfec tx free-running 8 khz signal. 1 slice 1?dwfec tx free-running 8 khz signal. 0 slice 0?dwfec tx free-running 8 khz signal.
agere systems inc. 177 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 38 microprocessor interface (continued) 38.11 general purpose input/output (gpio) (continued) table 153. gpio register summary function register name (first occurrence) register bits qty. 1st addr (hex) gpio configuration 0 (for gpi pins 47:32) dev_gpi_cfg0 (r/w) dev_gpio_dir0 1 0120 gpio configuration 1 (for gpi pins 31:16) dev_gpi_cfg1 (r/w) dev_gpio_dir1 1 0121 gpio configuration 2 (for gpi pins 15:0) dev_gpi_cfg2 (r/w) dev_gpio_dir2 1 0122 gpi interrupt polarity configuration 0 (for gpi pins 47:32) dev_gpi_int_pol0 (r/w) dev_gpi_int_pol0 1 0123 gpi interrupt polarity configuration 1 (for gpi pins 31:16) dev_gpi_int_pol1 (r/w) dev_gpi_int_pol1 1 0124 gpi interrupt polarity configuration 2 (for gpi pins 15:0) dev_gpi_int_pol2 (r/w) dev_gpi_int_pol2 1 0125 gpi interrupt type configuration 0 (for gpi pins 7:0) dev_gpi_int_typ0 (r/w) dev_gpi[7:0]_int_typ[1:0] 1 0126 gpi interrupt type configuration 1 (for gpi pins 15:8) dev_gpi_int_typ1 (r/w) dev_gpi[15:8]_int_typ[1:0] 1 0127 gpi interrupt type configuration 2 (for gpi pins 23:16) dev_gpi_int_typ2 (r/w) dev_gpi[23:16]_int_typ[1:0] 1 0128 gpi interrupt type configuration 3 (for gpi pins 31:24) dev_gpi_int_typ3 (r/w) dev_gpi[31:24]_int_typ[1:0] 1 0129 gpi interrupt type configuration 4 (for gpi pins 39:32) dev_gpi_int_typ4 (r/w) dev_gpi[39:32]_int_typ[1:0] 1 012a gpi interrupt type configuration 5 (for gpi pins 47:40) dev_gpi_int_typ5 (r/w) dev_gpi[47:40]_int_typ[1:0] 1 012b gpo output value 0 (for gpo pins 47:32) dev_gpo_val0 (r/w) dev_gpo_val0 1 012c gpo output value 1 (for gpo pins 31:16) dev_gpo_val1 (r/w) dev_gpo_val1 1 012d gpo output value 2 (for gpo pins 15:0) dev_gpo_val2 (r/w) dev_gpo_val2 1 012e gpo selection 0 (for gpo pins 3:0) dev_gpo_sel0 (r/w) dev_gpo[3:0]_sel[3:0] 1 012f gpo selection 1 (for gpo pins 7:4) dev_gpo_sel1 (r/w) dev_gpo[7:4]_sel[3:0] 1 0130
178 178 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface gpo selection 2 (for gpo pins 11:8) dev_gpo_sel2 (r/w) dev_gpo[11:8]_sel[3:0] 1 0131 gpo selection 3 (for gpo pins 15:12) dev_gpo_sel3 (r/w) dev_gpo[15:12]_sel[3:0] 1 0132 gpi interrupt alarm 0 (for gpi pins 47:32) dev_gpi_alarm0 (w1c) dev_gpi_a0 1 018 gpi interrupt alarm 1 (for gpi pins 31:16) dev_gpi_alarm1 (w1c) dev_gpi_a1 1 019 gpi interrupt alarm 2 (for gpi pins 15:0) dev_gpi_alarm2 (w1c) dev_gpi_a2 1 01a gpi interrupt mask 0 (for gpi pins 47:32) dev_gpi_mask0 (r/w) dev_gpi_m0 1 047 gpi interrupt mask 1 (for gpi pins 31:16) dev_gpi_mask1 (r/w) dev_gpi_m1 1 048 gpi interrupt mask 2 (for gpi pins 15:0) dev_gpi_mask2 (r/w) dev_gpi_m2 1 049 gpi interrupt persistency 0 (for gpi pins 47:32) dev_gpi_persist0 (ro) dev_gpi_p0 1 074 gpi interrupt persistency 1 (for gpi pins 31:16) dev_gpi_persist1 (ro) dev_gpi_p1 1 075 gpi interrupt persistency 2 (for gpi pins 15:0) dev_gpi_persist2 (ro) dev_gpi_p2 1 076 gpi interrupt raw state 0 (for gpi pins 47:32) dev_gpi_state0 (ro) dev_gpi0 1 094 gpi interrupt raw state 1 (for gpi pins 31:16) dev_gpi_state1 (ro) dev_gpi1 1 095 gpi interrupt raw state 2 (for gpi pins 15:0) dev_gpi_state2 (ro) dev_gpi2 1 096 38 microprocessor interface (continued) 38.11 general purpose input/output (gpio) (continued) table 153. gpio register summary (continued) function register name (first occurrence) register bits qty. 1st addr (hex)
agere systems inc. 179 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 39 tfec primary clock inputs the following table lists the possible tfec modes and the clocks (primary inputs) needed for each mode. the first column (mode) lists all the commonly used modes of the device. for each of these modes there is a reference (hyperlink) to the figures in the data sheet listed in the second column (figure number), if one exists. the receive line clock primary input (rclkli 3-2-1-0), as well as the total receive line rate (rx-line bandwidth), are listed in columns 3 and 4, respectively. the same listing is repeated for receive system, transmit line, and transmit system in subsequent columns. in regenerator mode, loopback is on the system side; for weak fec, this loopback could be before or after the elastic store on the system side. only commonly used modes are listed below. the bidirec- tional mode does not use the elastic store in dwfec. abbreviations used are listed below: strong: strong fec only , can be fec or digital wrapper mode. weak: weak fec only . x: clock input need not be present. p: clock input needs to be present. table 154. tfec clock setup mode figure number rclkli 3-2-1-0 rx-line bandwidth rclksi 3-2-1-0 rx-system bandwidth tclkli 3-2-1-0 tx-line bandwidth tclksi 3-2-1-0 tx-system bandwidth terminal [rx/tx symmetric; 16 bits at 622 mhz/666 mhz] strong 10 gbits/s 12/14 x-x-x-p 1 x 10.666 x-x-x-p 1 x 09.953 x-x-x-p 1 x 10.666 x-x-x-p 1 x 9.953 strong 2.5 gbits/s 12/14 p-p-p-p 4 x 2.666 p-p-p-p 4 x 2.488 p-p-p-p 4 x 2.666 p-p-p-p 4 x 2.488 strong bidirectional 10 gbits/s 16 x-x-x-p 1 x 10.666 ? 1 x 10.666 ? 1 x 10.666 x-x-x-p 1 x 10.666 strong bidirectional 2.5 gbits/s 16 p-p-p-p 4 x 2.666 ? 4 x 2.666 ? 4 x 2.666 p-p-p-p 4 x 2.666 weak 10 gbits/s 17 x-x-x-p 1 x 9.953 ? 1 x 9.953 ? 1 x 9.953 x-x-x-p 1 x 9.953 weak 2.5 gbits/s 17 p-p-p-p 4 x 2.488 ? 4 x 2.488 ? 4 x 2.488 p-p-p-p 4 x 2.488 strong and weak 10 gbits/s 19/21 x-x-x-p 1 x 10.666 x-x-x-p 1 x 9.953 x-x-x-p 1 x 10.666 x-x-x-p 1 x 9.953 strong and weak 2.5 gbits/s 19/21 p-p-p-p 4 x 2.666 p-p-p-p 4 x 2.488 p-p-p-p 4 x 2.666 p-p-p-p 4 x 2.488 regenerator [rx/tx symmetric, internal loopback on the system; 16 bits at 622 mhz/666 mhz] strong 10 gbits/s 13/15 x-x-x-p 1 x 10.666 x-x-x-p ? ? 1 x 10.666 ? ? strong 2.5 gbits/s 13/15 p-p-p-p 4 x 2.666 p-p-p-p ? ? 4 x 2.666 ? ? strong bidirectional 10 gbits/s ? x-x-x-p 1 x 10.666 ? ? ? 1 x 10.666 ? ? strong bidirectional 2.5 gbits/s ? p-p-p-p 4 x 2.666 ? ? ? 4 x 2.666 ? ? weak 10 gbits/s before lb es 18 x-x-x-p 1 x 9.953 ? ? ? 1 x 9.953 ? ? weak 2.5 gbits/s before lb es 18 p-p-p-p 4 x 2.488 ? ? ? 4 x 2.488 ? ? strong and weak 10 gbits/s 20 x-x-x-p 1 x 10.666 x-x-x-p ? ? 1 x 9.953 ? ? strong and weak 2.5 gbits/s 20 p-p-p-p 4 x 2.666 p-p-p-p ? ? 4 x 2.488 ? ? multiplex mode terminal [weak fec only, 2.5 gbits/s to 10 gbits/s/10 gbits/s to 2.5 gbits/s; 16 bits at 622 mhz/666 mhz] 10gline_2g5system 22 x-x-x-p 1 x 9.953 ? 4 x 2.488 ? 1 x 9.953 x-x-x-p 4 x 2.488 strong 10gline_2g5system 22 x-x-x-p 1 x 10.666 x-x-x-p 4 x 2.488 x-x-x-p 1 x 10.666 x-x-x-p 4 x 2.488 single 2.5 gbits/s terminal [16 bits at 155 mhz/166 mhz] strong 2.5 gbits/s 23 x-x-x-p 1 x 2.666 x-x-x-p 1 x 2.488 x-x-x-p 1 x 2.666 x-x-x-p 1 x 2.488 strong bidirectional 2.5 gbits/s 23 x-x-x-p 1 x 2.666 ? 1 x 2.666 ? 1 x 2.666 x-x-x-p 1 x 2.666 weak 2.5 gbits/s 23 x-x-x-p 1 x 2.488 ? 1 x 2.488 ? 1 x 2.488 x-x-x-p 1 x 2.488 strong and weak 2.5 gbits/s 23 x-x-x-p 1 x 2.666 x-x-x-p 1 x 2.488 x-x-x-p 1 x 2.666 x-x-x-p 1 x 2.488 single 2.5 gbits/s regenerator [16 bits at 155 mhz/166 mhz] strong 2.5 gbits/s 23 x-x-x-p 1 x 2.666 x-x-x-p ? ? 1 x 2.666 ? ? strong bidirectional 2.5 gbits/s 23 x-x-x-p 1 x 2.666 ? ? ? 1 x 2.666 ? ? weak 2.5 gbits/s 23 x-x-x-p 1 x 2.488 ? ? ? 1 x 2.488 ? ? strong and weak 2.5 gbits/s 23 x-x-x-p 1 x 2.666 x-x-x-p ? ? 1 x 2.666 ? ?
180 180 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 40 tfec clock multiplexers the clock multiplexers listed below refer to figure 24 on page 30. the values shown below are those for dev_ctl_clkmuxn_sm. when programming the clock multiplexer registers, the clock inversion control bit should be set to 0x0 (no inversion) under all conditions. 40.1 clock multiplexers and register bits selection clock mux a: dev_ctl_clkmux0_sn [10:8] clock mux b: dev_ctl_clkmux4_sn [02:0] clock mux c: dev_ctl_clkmux0_sn [02:0] clock mux d: dev_ctl_clkmux1_sn [10:8] clock mux e: dev_ctl_clkmux1_sn [02:0] clock mux f: dev_ctl_clkmux2_sn [10:8] clock mux g: dev_ctl_clkmux2_sn [02:0] clock mux h: dev_ctl_clkmux3_sn [10:8] clock mux i: dev_ctl_clkmux4_sn [10:8] clock mux j: dev_ctl_clkmux3_sn [02:0] 40.2 clock selection 0x00: ground 0x01: transmit system clock 0x02: receive system clock 0x03: transmit line clock 0x04: receive line clock
agere systems inc. 181 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 40 tfec clock multiplexers (continued) 40.2 clock selection (continued) table 155. tfec clock multiplexers programming mode figure number a 1 bcdefgh ij 1 terminal [rx/tx symmetric; 16 bits at 622 mhz/666 mhz] strong 10 gbits/s 12/14 0x03 0x03 0x03 0x01 0x00 0x04 0x02 0x00 0x02 0x02 strong 2.5 gbits/s 12/14 0x03 0x03 0x03 0x01 0x00 0x04 0x02 0x00 0x02 0x02 strong bidirectional 10 gbits/s 16 0x01 0x01 0x01 0x01 0x00 0x04 0x00 0x00 0x04 0x04 strong bidirectional 2.5 gbits/s 16 0x01 0x01 0x01 0x01 0x00 0x04 0x00 0x00 0x04 0x04 weak 10 gbits/s 17 0x01 0x01 0x00 0x00 0x01 0x00 0x00 0x04 0x04 0x04 weak 2.5 gbits/s 17 0x01 0x01 0x00 0x00 0x01 0x00 0x00 0x04 0x04 0x04 strong and weak 10 gbits/s 19/21 0x03 0x03 0x03 0x01 0x01 0x04 0x02 0x02 0x02 0x02 strong and weak 2.5 gbits/s 19/21 0x03 0x03 0x03 0x01 0x01 0x04 0x02 0x02 0x02 0x02 regenerator [rx/tx symmetric, internal loopback on the system; 16 bits at 622 mhz/666 mhz] strong 10 gbits/s 13/15 0x04 0x04 0x04 0x02 0x00 0x04 0x02 0x00 0x00 0x00 strong 2.5 gbits/s 13/15 0x04 0x04 0x04 0x02 0x00 0x04 0x02 0x00 0x00 0x00 strong bidirectional 10 gbits/s ? 0x04 0x04 0x04 0x00 0x00 0x04 0x00 0x00 0x00 0x00 strong bidirectional 2.5 gbits/s ? 0x04 0x04 0x04 0x00 0x00 0x04 0x00 0x00 0x00 0x00 weak 10 gbits/s 18 0x04 0x04 0x00 0x00 0x04 0x00 0x00 0x04 0x00 0x00 weak 2.5 gbits/s 18 0x04 0x04 0x00 0x00 0x04 0x00 0x00 0x04 0x00 0x00 strong and weak 10 gbits/s before lb es 20 0x04 0x04 0x04 0x02 0x02 0x04 0x02 0x02 0x00 0x00 strong and weak 2.5 gbits/s before lb es 20 0x04 0x04 0x04 0x02 0x02 0x04 0x02 0x02 0x00 0x00 multiplex mode terminal [weak fec only, 2.5 gbits/s to 10 gbits/s/10 gbits/s to 2.5 gbits/s; 16 bits at 622 mhz/666 mhz] 10gline_2g5system 22 0x01 0x01 0x00 0x00 0x01 0x00 0x00 0x04 0x04 0x04 strong 10gline_2g5system 22 0x03 0x03 0x03 0x01 0x01 0x04 0x02 0x02 0x02 0x02 single 2.5 gbits/s terminal [16 bits at 155 mhz/166 mhz] strong 2.5 gbits/s 23 0x03 0x03 0x03 0x01 0x00 0x04 0x02 0x00 0x02 0x02 strong bidirectional 2.5 gbits/s 23 0x01 0x01 0x01 0x01 0x00 0x04 0x00 0x00 0x04 0x04 weak 2.5 gbits/s 23 0x01 0x01 0x00 0x00 0x01 0x00 0x00 0x04 0x04 0x04 strong and weak 2.5 gbits/s 23 0x03 0x03 0x03 0x01 0x01 0x04 0x02 0x02 0x02 0x02 single 2.5 gbits/s regenerator [16 bits at 155 mhz/166 mhz] strong 2.5 gbits/s 23 0x04 0x04 0x04 0x02 0x00 0x04 0x02 0x00 0x00 0x00 strong bidirectional 2.5 gbits/s 23 0x04 0x04 0x04 0x00 0x00 0x04 0x00 0x00 0x00 0x00 weak 2.5 gbits/s 23 0x04 0x04 0x00 0x00 0x04 0x00 0x00 0x04 0x00 0x00 strong and weak 2.5 gbits/s 23 0x04 0x04 0x04 0x02 0x02 0x04 0x02 0x02 0x00 0x00 1. for clock multiplexers a and j, in 10 gbits/s mode, only slice 0 needs to be programmed.
182 182 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 41 tfec data multiplexers the data multiplexers listed below refers to figure 24 on page 30. the values shown below are those for dev_ctl_dmux_sm. 41.1 data multiplexers and register bits selection data mux k: dev_ctl_dmux_sn [5:4] data mux l: dev_ctl_dmux_sn [7:6] data mux m: dev_ctl_dmux_sn [8] data mux n: dev_ctl_dmux_sn [3] data mux o: dev_ctl_dmux_sn [2] data mux p: dev_ctl_dmux_sn [1:0] table 156. tfec data multiplexer programming a value of 0xxx indicates a do not care condition. it could be set to 0x00. mode figure number klmnop terminal [rx/tx symmetric, 16 bits at 622 mhz/666 mhz] strong 10 gbits/s 12/14 0x00 0x01 0xxx 0xxx 0x00 0x01 strong 2.5 gbits/s 12/14 0x00 0x01 0xxx 0xxx 0x00 0x01 strong bidirectional 10 gbits/s 16 0x00 0x01 0xxx 0xxx 0x01 0x01 strong bidirectional 2.5 gbits/s 16 0x00 0x01 0xxx 0xxx 0x01 0x01 weak 10 gbits/s 17 0x01 0xxx 0x00 0x01 0xxx 0x00 weak 2.5 gbits/s 17 0x01 0xxx 0x00 0x01 0xxx 0x00 strong and weak 10 gbits/s 19/21 0x00 0x00 0x00 0x00 0xxx 0x00 strong and weak 2.5 gbits/s 19/21 0x00 0x00 0x00 0x00 0xxx 0x00 regenerator [rx/tx symmetric, internal loopback on the system; 16 bits at 622 mhz/666 mhz] strong 10 gbits/s 1 13/15 0x00 0x02 0xxx 0xxx 0xxx 0xxx strong 2.5 gbits/s 1 13/15 0x00 0x02 0xxx 0xxx 0xxx 0xxx strong bidirectional 10 gbits/s 2 ? 0x00 0xxx 0xxx 0xxx 0xxx 0xxx strong bidirectional 2.5 gbits/s 2 ? 0x00 0xxx 0xxx 0xxx 0xxx 0xxx weak 10 gbits/s 3 18 0x01 0xxx 0xxx 0x01 0xxx 0xxx weak 2.5 gbits/s 3 18 0x01 0xxx 0xxx 0x01 0xxx 0xxx strong and weak 10 gbits/s 3 20 0x00 0x00 0xxx 0x00 0xxx 0xxx strong and weak 2.5 gbits/s 3 20 0x00 0x00 0xxx 0x00 0xxx 0xxx notes: 1. loopback assumes at data mux l. 2. loopback assumes after dw inside dwfec. 3. loopback assumes inside sonfec.
agere systems inc. 183 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 1. loopback assumes at data mux l. 2. loopback assumes after dw inside dwfec. 3. loopback assumes before data mux m, inside sonfec. 42 tfec phase detectors 42.1 clock division select 0x0: 622 mhz clock, division by 14 or 79. 0x1: 666 mhz clock, division by 15 or 85. 42.2 clock selection 0x00: ground 0x01: transmit system clock 0x02: transmit line clock 0x03: receive system clock 0x04: receive line clock multiplex mode terminal [weak fec only, 2.5 gbits/s to 10 gbits/s/10 gbits/s to 2.5 gbits/s; 16 bits at 622 mhz/666 mhz] 10gline_2g5system 22 0x01 0xxx 0x00 0x01 0xxx 0x00 strong 10gline_2g5system 22 0x00 0x00 0x00 0x00 0xxx 0x00 single 2.5 gbits/s terminal [16 bits at 155 mhz/166 mhz] strong 2.5 gbits/s 23 0x00 0x01 0xxx 0xxx 0x00 0x01 strong bidirectional 2.5 gbits/s 23 0x00 0x01 0xxx 0xxx 0x01 0x01 weak 2.5 gbits/s 23 0x01 0xxx 0x00 0x01 0xxx 0x00 strong and weak 2.5 gbits/s 23 0x00 0x00 0x00 0x00 0xxx 0x00 single 2.5 gbits/s regenerator [16 bits at 155 mhz/166 mhz] strong 2.5 gbits/s 1 23 0x00 0x02 0xxx 0xxx 0xxx 0xxx strong bidirectional 2.5 gbits/s 2 23 0x00 0xxx 0xxx 0xxx 0xxx 0xxx weak 2.5 gbits/s 3 23 0x01 0xxx 0xxx 0x01 0xxx 0xxx strong and weak 2.5 gbits/s 3 23 0x00 0x00 0xxx 0x00 0xxx 0xxx table 156. tfec data multiplexer programming (continued) a value of 0xxx indicates a do not care condition. it could be set to 0x00. mode figure number klmnop 41 tfec data multiplexers (continued)
184 184 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 42 tfec phase detectors (continued) 42.2 clock selection (continued) table 157. tfec phase detectors programming the polarity of the phase detectors is programmed to no inversion by default. mode figure number rclkli rclksi receive pd controls tclkli tclksi transmit pd controls variable reference variable reference div sel div sel div sel div sel terminal [rx/tx symmetric; 16 bits at 622 mhz/666 mhz] strong 10 gbits/s 12/14 666 mhz 622 mhz 0x0 0x03 0x1 0x04 666 mhz 622 mhz 0x1 0x02 0x0 0x01 strong 2.5 gbits/s 12/14 666 mhz 622 mhz 0x0 0x03 0x1 0x04 666 mhz 622 mhz 0x1 0x02 0x0 0x01 strong bidirectional 10 gbits/s 16 666 mhz ? ? ? ? ? ? 666 mhz ? ? ? ? strong bidirectional 2.5 gbits/s 16 666 mhz ? ? ? ? ? ? 666 mhz ? ? ? ? weak 10 gbits/s 17 622 mhz ? ? ? ? ? ? 622 mhz ? ? ? ? weak 2.5 gbits/s 17 622 mhz ? ? ? ? ? ? 622 mhz ? ? ? ? strong and weak 10 gbits/s 19/21 666 mhz 622 mhz 0x0 0x03 0x1 0x04 666 mhz 622 mhz 0x1 0x02 0x0 0x01 strong and weak 2.5 gbits/s 19/21 666 mhz 622 mhz 0x0 0x03 0x1 0x04 666 mhz 622 mhz 0x1 0x02 0x0 0x01 regenerator [rx/tx symmetric, internal loopback on the system; 16 bits at 622 mhz/666 mhz] strong 10 gbits/s 13/15 666 mhz 622 mhz 0x0 0x03 0x1 0x04 ? ? ? ? ? ? strong 2.5 gbits/s 13/15 666 mhz 622 mhz 0x0 0x03 0x1 0x04 ? ? ? ? ? ? strong bidirectional 10 gbits/s ? 666 mhz ? ? ? ? ? ? ? ? ? ? ? strong bidirectional 2.5 gbits/s ? 666 mhz ? ? ? ? ? ? ? ? ? ? ? weak 10 gbits/s before lb es 18 622 mhz ? ? ? ? ? ? ? ? ? ? ? weak 2.5 gbits/s before lb es 18 622 mhz ? ? ? ? ? ? ? ? ? ? ? weak 10 gbits/s through lb es 18 622 mhz ? ? ? ? ? 622 mhz ? 0x0 0x02 0x0 0x04 weak 2.5 gbits/s through lb es 18 622 mhz ? ? ? ? ? 622 mhz ? 0x0 0x02 0x0 0x04 strong and weak 10 gbits/s before lb es 20 666 mhz 622 mhz 0x0 0x03 0x1 0x04 ? ? ? ? ? ? strong and weak 2.5 gbits/s before lb es 20 666 mhz 622 mhz 0x0 0x03 0x1 0x04 ? ? ? ? ? ? strong and weak 10 gbits/s through lb es 20 666 mhz 622 mhz 0x0 0x03 0x1 0x04 622 mhz ? 0x0 0x02 0x1 0x04 strong and weak 2.5 gbits/s through lb es 20 666 mhz 622 mhz 0x0 0x03 0x1 0x04 622 mhz ? 0x0 0x02 0x1 0x04 multiplex mode terminal [weak fec only, 2.5 gbits/s to 10 gbits/s/10 gbits/s to 2.5 gbits/s; 16 bits at 622 mhz/666 mhz] 10gline_2g5system 22 622 mhz ? ? ? ? ? ? 622 mhz ? ? ? ? strong 10gline_2g5system 22 666 mhz 622 mhz 0x0 0x03 0x1 0x04 666 mhz 622 mhz 0x1 0x02 0x0 0x01 single 2.5 gbits/s terminal [16 bits at 155 mhz/166 mhz] strong 2.5 gbits/s 23 166 mhz 155 mhz 0x0 0x03 0x1 0x04 166 mhz 155 mhz 0x1 0x02 0x0 0x01 strong bidirectional 2.5 gbits/s 23 166 mhz ? ? ? ? ? ? 166 mhz ? ? ? ? weak 2.5 gbits/s 23 155 mhz ? ? ? ? ? ? 155 mhz ? ? ? ? strong and weak 2.5 gbits/s 23 166 mhz 155 mhz 0x0 0x03 0x1 0x04 166 mhz 155 mhz 0x1 0x02 0x0 0x01 single 2.5 gbits/s regenerator [16 bits at 155 mhz/166 mhz] strong 2.5 gbits/s 23 166 mhz 155 mhz 0x0 0x03 0x1 0x04 ? ? ? ? ? ? strong bidirectional 2.5 gbits/s 23 166 mhz ? ? ? ? ? ? ? ? ? ? ? weak 2.5 gbits/s before lb es 23 155 mhz ? ? ? ? ? ? ? ? ? ? ? weak 2.5 gbits/s through lb es 23 155 mhz ? ? ? ? ? 155 mhz ? 0x0 0x02 0x0 0x04 strong and weak 2.5 gbits/s before lb es 23 166 mhz 155 mhz 0x0 0x03 0x1 0x04 ? ? ? ? ? ? strong and weak 2.5 gbits/s through lb es 23 166 mhz 155 mhz 0x0 0x03 0x1 0x04 155 mhz ? 0x0 0x02 0x1 0x04
agere systems inc. 185 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 43 tfec loopbacks the valid loopback configurations of tfec are listed below. refer to figure 24 on page 30. the high-speed inter- face loopbacks are at 78 mhz or 83 mhz. these loopbacks are essentially loops through the high-speed multi- plexer and demultiplexer blocks which could be operated at either of these clock frequencies. in all these modes, if an elastic store is present, any other clock could be used as long as its frequency matches that of the clock on the other side of the elastic store. the settings shown below are to be considered as guidelines only. as an example, it is possible to initiate two loopbacks inside the device, one within dwfec (rdw2tdw_lb) and another within sonfec (tline2rline_lb), simultaneously. such combinations are not listed in table 158. the primary input tfrmli can only be used if the tclkli is present. however, tclkli could be used directly or as a substitute for any other clock via rclksi if the use of tfrmli is desired. in 10 gbits/s mode, only slice 0 of clock multiplexers a and j needs to be programmed. table 158. tfec loopback programming loopback (active signal) primary clocks clock multiplexers data multiplexers a/b c d e f g h i/j k l m n o p receive high-speed interface [at 78 mhz/83 mhz] loopbacks (dwfec and sonfec are disabled) r2tf_lb rclkli 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0xxx 0xxx 0xxx 0xxx 0xxx receive dwfec only loopbacks (sonfec is disabled) rdw2tdw_lb rclkli 0x04 0x04 0x00 0x00 0x04 0x00 0x00 0x00 0x00 0xxx 0xxx 0xxx 0xxx 0xxx res2tes_lb rclkli rclksi 0x04 0x04 0x02 0x00 0x04 0x02 0x00 0x00 0x00 0x02 0xxx 0xxx 0xxx 0xxx receive sonfec only loopbacks (dwfec disabled) rsys2tsys_lb rclkli 0x04 0x00 0x00 0x04 0x00 0x00 0x04 0x00 0x01 0xxx 0xxx 0x01 0xxx 0xxx receive dwfec and sonfec loopbacks rsys2tsys_lb rclkli rclksi tclkli 0x03 0x03 0x02 0x02 0x04 0x02 0x02 0x00 0x00 0x00 0xxx 0x00 0xxx 0xxx transmit high-speed interface [at 78 mhz/83 mhz] loopbacks (dwfec and sonfec are disabled) t2rf_lb tclksi 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0xxx 0xxx 0xxx 0xxx 0xxx 0x02 transmit sonfec only loopbacks (dwfec is disabled) tline2rline_lb tclksi 0x00 0x00 0x00 0x01 0x00 0x00 0x01 0x01 0xxx 0xxx 0x00 0xxx 0xxx 0x00 transmit dwfec only loopbacks (sonfec is disabled) tdw2rdw_lb 1 1. this loopback assumes dwes is bypassed (bidirectional mode); tfrmli cannot be used to generate fec/dw frames. tclksi 0x00 0x01 0x00 0x00 0x01 0x00 0x00 0x01 0xxx 0x01 0xxx 0xxx 0x01 0x01 tdw2rdw_lb 2 2. this loopback assumes dwes is present; tfrmli could be used to generate fec/dw frames. tclksi tclkli rclksi 0x00 0x03 0x01 0x00 0x03 0x02 0x00 0x02 0xxx 0x01 0xxx 0xxx 0x00 0x01 trsen2rrsde_lb 1 tclksi 0x00 0x01 0x00 0x00 0x01 0x00 0x00 0x01 0xxx 0x01 0xxx 0xxx 0x01 0x01 trsen2rrsde_lb 2 tclksi tclkli rclksi 0x00 0x03 0x01 0x00 0x03 0x02 0x00 0x02 0xxx 0x01 0xxx 0xxx 0x00 0x01 transmit dwfec and sonfec loopbacks tdw2rdw_lb tclksi tclkli rclksi 0x00 0x03 0x01 0x01 0x03 0x02 0x02 0x02 0xxx 0x00 0x00 0x00 0xxx 0x00 trsen2rrsde_lb tclksi tclkli rclksi 0x00 0x03 0x01 0x01 0x03 0x02 0x02 0x02 0xxx 0x00 0x00 0x00 0xxx 0x00
186 186 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 44 tfec valid modes the following truth table illustrates possible rx/tx modes in the tfec0410g. any combinations of these modes could be used. however care must be taken to set up the clocks in these modes. refer to the section 40, tfec clock multiplexers, on page 180 to see the following settings: dwfec: strong fec (fec/dw mode) sonfec: weak fec dwes: dwfec elastic store 44.1 general conditions on primary clock inputs both rclkli and tclksi need to be present in all modes, except loopback/regenerator modes. if dwfec is used along with sonfec and/or dwes, then both tclkli and rclksi need to be present. if dwfec is used with no dwes or sonfec, then no other clocks need be present. in case of multiplexing (10 gbits/s ? 2.5 gbits/s), all four 2.5 gbits/s signals are to be bit synchronous to the same clock via tclksi[0]. figure 55. tfec rx/tx possible modes dwfec?no dwes system line 1 x 10.666 1 x 09.953 4 x 02.666 4 x 02.488 1 x 10.666 1 x 09.953 4 x 02.666 4 x 02.488 dwfec + dwes dwfec + sonfec invalid dwfec + sonfec invalid invalid invalid invalid sonfec [t x only] invalid invalid sonfec sonfec dwfec?no dwes dwfec + dwes dwfec + sonfec sonfec
agere systems inc. 187 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 45 outline diagram 45.1 792-pin pbgam1th 40.00 0.20 40.00 a1 ball t d h al f k b p m l j ah r c e y n u an g ad v am aj ag ae ac aa w ap ak af ab ar a a1 ball corner 0.20 corner 38.70 19 30 26 28 24 32 22 20 18 4 6 8 10 12 14 16 2 34 5 23 25 7 31 29 15 21 3 27 11 17 9 13 1 35 33 au at av aw 36 38 37 39 1.00 35.35 max + 0.70 ? 0.05 a1 ball pad indicator available marking area 17.72 8 x 4.33 4 x 45 35.35 max 38.70 + 0.70 ? 0.05 country of origin indicator chamfer 1.17 0.05 seating plane solder ball 0.61 0.06 0.20 2.28 0.21 0.50 0.10 30 typ 0.50 r, 3 places 1.00 1.00
188 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 46 list of acronyms a adm add/drop multiplexer ais alarm indication signal ais-l line alarm indication signal api application program interface apll analog phase locked loop ar alarm register au administrative unit (sdh naming for frames) b b1, b2, b3 error count bits bar base address register bch bose-chaudhuri-hocquenguem (weak fec cyclic code) bdi backward defect indication bdi-o backward defect indication overhead bdi-p backward defect indication payload bei backward error indication ber bit error rate bi backward indication bim byte interleaved multiplexer bip bit interleaved parity bip-8 bit interleaved parity level 8 bist built-in self-test bit binary digit bli backward line indication blsr bidirectional line switch ring bits/s bits per second bs boundary scan c c2 expected payload label bit cbr constant bit rate cdr clock data recovery cm common mode or configuration management or connection monitoring cmep connection monitoring end point cmf common-mode failure cml current-mode logic cmoh connection monitoring overhead cmr common mode rejection cms current-mode switching cmv common-mode voltage cntd continuous n-times detect cor clear on read corba common object request broker architecture cow clear on write cpt cell pointer table cpu central processing unit crc cyclic redundancy check or cyclic redundancy code cv coding violation cv-l line coding violation cv-p path coding violation cv-s section coding violation d dcc data communications channel dll delay-locked loop dpll dedicated phase-locked loop dram dynamic random access memory dsp digital signal processor dw digital wrapper dwac digital wrapper access channel dwdm dense wavelength division multiplexing dwsfec digital wrapper enhanced forward error correction e efec enhanced forward error correction es errored second or elastic store esd electrostatic discharge esf extended superframe esi end system identifier evt egress vc table extest external test exti expected trace identifier f fae field application engineer fas frame alignment signal fcbga flip-chip ball-grid array fcs frame check sequence fdi forward defect indication fdi-o forward defect indication overhead fdi-p forward defect indication payload fe framing (bit) error febe far-end block error fec forward error correction fifo first in, first out fm frequency modulation fpga field programmable gate array fs fixed stuff fsi fec status indicator fsm finite state machine ftfl fault type and fault location
agere systems inc. 189 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 46 list of acronyms (continued) g gbe gigabit ethernet gnd ground gpi general purpose input gpio general purpose input/output gpo general purpose output grst global reset gsr global set/reset h h1, h2 sonet signal payload pointer bits hdlc high-level data link control hec header error correction or header error control hsi high-speed interface hw hardware i i/o input/output iadi intra-domain interface iae incoming alignment error idi initial domain identifier irdi inter-domain interface irq interrupt request isr interrupt status register itu international telecommunications union j j1 trace byte jedec joint electronic devices engineering council jc stuff control byte jtag joint test access group k k1, k2 aps bits of sonet signal l ladi intradomain interface lan local area network lapi low-level application programming interface lb loopback lck locked led light emitting diode loc loss of clock lof loss of frame lofa loss of frame alignment loh line overhead lol loss of lock lom loss of multiframe alignment lop loss of pointer los loss of signal lotc loss of transmit clock lrdi interdomain interface lsb least significant bit/byte lsn least significant nibble lte line terminating equipment lv low voltage lvds low-voltage differential signal m mfas multiframe alignment signal mpi microprocessor interface mpif master processor interface ms multiplex section msb most significant bit/byte msi multiplex structure identifier msn most significant nibble mutex mutual exclusion mux multiplex or multiplexor n njo negative justification offset (negative justification byte) nrz nonreturn to zero nsa non-service affecting n-time detect a received value remains the same for n consecutive frames.
190 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 46 list of acronyms (continued) o oa&m operations administration and maintenance och optical channel (single) oci open connection indication oduk optical channel data unit oh overhead ohp overhead processor ohpi overhead processor insertion ohpm overhead processor monitoring omsn optical multiplex section overhead oms optical multiplexing section omu optical multiplexing unit onni optical transport network node interface ooa out of alignment oof out of frame oom out of multiframe alignment oos optical transport module overhead signal opu optical channel payload unit osc optical supervisory channel osi open system interconnect oth optical transport hierarchy otm optical transport module otm-0 optical transport module of order 0 otn optical transport network ots optical transmission section otsn optical transmission section overhead otuk optical channel transport unit p pa persistency alarm pbga plastic ball grid array pbgam plastic ball grid array multilayer pclk microprocessor clock pd phase detector pdi payload defect indication phy physical layer pjo positive justification offset byte pll phase-locked loop pm performance monitoring pmclk performance monitoring clock pmoh path monitoring overhead pn pseudo-random noise sequence or pseudo-random number (i.e., pn29) pnz positive/negative/zero poac path overhead access channel poh path overhead pos packet-over-sonet/sdh p-p peak to peak pp pointer processor ppll programmable phase-locked loop pram pointer random access memory prbs pseudo-random bit sequence psi payload structure identifier q qos quality of service r r/w read/write rai remote alarm indication rdi remote defect indicator rdi-l line remote defect indication rei remote error indication rei-l line remote error indication res reserved rn random number ro read only rs reed solomon (strong fec) rw read/write rx receive rz return to zero
agere systems inc. 191 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 46 list of acronyms (continued) s sa service affecting sclk system clock sd signal degrade sdh synchronous digital hierarchy sef severely errored frame serdes serializer/deserializer sf signal fail sfi serdes framer interface sfi-4 serdes framer interface level 4 sm section monitoring snmp simple network management protocol snr signal-to-noise ratio soh section overhead sonet synchronous optical network sonfec sonet forward error correction spa selected packet available spe sonet payload envelope spif slave processor interface stat status indication ste section terminating equipment swi software interrupt t ta transfer acknowledge t a ambient temperature tbd to be determined tc temperature coefficient or time constant or tandem connection t c case temperature tck test clock tcm tandem connection monitoring tcmoh tandem connection monitoring overhead tdi test data in tdm time division multiplexer tdmx transpose demultiplexer tdo test data out tea transfer error acknowledge tfec transmission forward error correcting tim trace identifier mismatch t j junction temperature tms test mode select toac transport overhead access channel toh transport overhead t prop propagation time trstn test reset (active low) ts time slot or tributary slot tsi time-slot interchange tsm tributary slot multiplexing tti trail trace identifier tx transmit u uneq unequipped uni user-network interface upsr unidirectional path switch ring utopia universal test and operations physical interface for atm v vbr variable bit rate vc virtual channel vci virtual connection indicator vco voltage-controlled oscillator vp virtual path vpi virtual path indicator vt virtual tributary vtg virtual tributary group w w1c write one clear wdm wavelength division multiplexing wrr weighted round robin x xpif external processor interface z z0 section overhead bit
192 192 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface list of objects object page object page a address ............................................................................ 169, 170 ais_cond_insert ...................................................................... 68 algn_inh ................................................................................... 131 aps_bypass .............................................................................. 157 b bch_alarm_s0 ......................................................................... 127 bch_ber_clr_limit_10 .......................................................... 127 bch_ber_clr_limit_4 ............................................................ 127 bch_ber_clr_limit_5 ............................................................ 127 bch_ber_clr_limit_6 ............................................................ 127 bch_ber_clr_limit_7 ............................................................ 127 bch_ber_clr_limit_8 ............................................................ 127 bch_ber_clr_limit_9 ............................................................ 127 bch_ber_dt_unit_10 ............................................................. 127 bch_ber_dt_unit_3 ............................................................... 127 bch_ber_dt_unit_4 ............................................................... 127 bch_ber_dt_unit_5 ............................................................... 127 bch_ber_dt_unit_6 ............................................................... 127 bch_ber_dt_unit_7 ............................................................... 127 bch_ber_dt_unit_8 ............................................................... 127 bch_ber_dt_unit_9 ............................................................... 127 bch_ber_dt_val_10 ............................................................... 127 bch_ber_dt_val_3 ................................................................. 127 bch_ber_dt_val_4 ................................................................. 127 bch_ber_dt_val_5 ................................................................. 127 bch_ber_dt_val_6 ................................................................. 127 bch_ber_dt_val_7 ................................................................. 127 bch_ber_dt_val_8 ................................................................. 127 bch_ber_dt_val_9 ................................................................. 127 bch_ber_report ................................................................... 127 bch_ber_set_limit_3 ............................................................ 127 bch_ber_set_limit_4 ............................................................ 127 bch_ber_set_limit_5 ............................................................ 127 bch_ber_set_limit_6 ............................................................ 127 bch_ber_set_limit_7 ............................................................ 127 bch_ber_set_limit_8 ............................................................ 127 bch_ber_set_limit_9 ............................................................ 127 bch_berclr10 ......................................................................... 127 bch_berclr4 ........................................................................... 127 bch_berclr5 ........................................................................... 127 bch_berclr6 ........................................................................... 127 bch_berclr7 ........................................................................... 127 bch_berclr8 ........................................................................... 127 bch_berclr9 ........................................................................... 127 bch_berdt10 ............................................................................ 127 bch_berdt3 .............................................................................. 127 bch_berdt4 .............................................................................. 127 bch_berdt5 .............................................................................. 127 bch_berdt6 .............................................................................. 127 bch_berdt7 .............................................................................. 127 bch_berdt8 .............................................................................. 127 bch_berdt9 .............................................................................. 127 bch_berset3 ........................................................................... 127 bch_berset4 ........................................................................... 127 bch_berset5 ........................................................................... 127 bch_berset6 ........................................................................... 127 bch_berset7 ........................................................................... 127 bch_berset8 ........................................................................... 127 bch_berset9 ........................................................................... 127 bch_dec_extract ................................................................. 124 bch_dec_fsi ............................................................................ 125 bch_dec_fsi_a ........................................................................ 125 bch_dec_fsi_m ....................................................................... 125 bch_dec_fsi_p ........................................................................ 125 bch_dec_mode ....................................................................... 125 bch_enc_insert ..................................................................... 122 bch_enc_mode ....................................................................... 122 bch_err_bitblk ..................................................................... 126 bch_err_bitcnt_l ................................................................. 126 bch_err_bitcnt_l_s0 .......................................................... 126 bch_err_bitcnt_u ................................................................ 126 bch_err_bitcnt_u_s0 .......................................................... 126 bch_err_blkcnt_l_s0 ......................................................... 126 bch_err_blkcnt_u_s0 ......................................................... 126 bch_err_prov_s0 ......................................................... 126, 127 bch_err_rpt_s0 .................................................................... 127 bch_mask_s0 ........................................................................... 127 bch_persist_s0 ..................................................................... 127 bch_prov_s0 ........................................................................... 122 bch_rx_alarm_s0 .................................................................. 125 bch_rx_ber_sd ...................................................................... 127 bch_rx_ber_sd_det ............................................................. 127 bch_rx_ber_sd_det_a ........................................................ 127 bch_rx_ber_sd_det_m ........................................................ 127 bch_rx_ber_sd_det_p ........................................................ 127 bch_rx_ber_sf ...................................................................... 127 bch_rx_ber_sf_det ............................................................. 127 bch_rx_ber_sf_det_a ......................................................... 127 bch_rx_ber_sf_det_m ........................................................ 127 bch_rx_ber_sf_det_p ......................................................... 127 bch_rx_mask_s0 .................................................................... 125 bch_rx_persist_s0 ............................................................... 125 bch_rx_state_s0 .................................................................. 125 bch_rxprov_s0 .............................................................. 124, 125 bch_state_s0 ......................................................................... 127 bch_tx_alarm_s0 .................................................................. 123 bch_tx_mask_s0 .................................................................... 123 bch_tx_persist_s0 ............................................................... 123 bch_tx_state_s0 ................................................................... 123 bch_txerr_col ...................................................................... 123 bch_txerr_finish ................................................................. 123 bch_txerr_finish_a ............................................................. 123 bch_txerr_finish_m ............................................................ 123 bch_txerr_finish_p ............................................................. 123 bch_txerr_mask_l ............................................................... 123 bch_txerr_mask_u .............................................................. 123 bch_txerr_maskl_s0 ........................................................... 123 bch_txerr_masku_s0 .......................................................... 123 bch_txerr_repeat ............................................................... 123 bch_txerr_repeat_s0 ........................................................ 123 bch_txerr_row .................................................................... 123 bch_txerr_rowcol_s0 ....................................................... 123 bch_txerr_skip ..................................................................... 123 bch_txerr_skip_s0 ............................................................... 123 bch_txerr_start ................................................................. 123 bch_txerr_start_s0 ........................................................... 123 bch_unc_blkcnt_l ............................................................... 126 bch_unc_blkcnt_u ............................................................... 126 bdi_tx ........................................................................................... 46 bdi_txl ................................................................................... 46, 47
agere systems inc. 193 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface list of objects (continued) object page object page bei_rxl ............................................................................. 48, 49, 50 bei_txl ................................................................................... 46, 47 bip_rxl ............................................................................. 48, 49, 50 bip_txl ................................................................................... 46, 47 bypass ....................................................................................... 131 c cs_n .................................................................................... 169, 170 d data .................................................................................... 169, 170 descrm_dis .............................................................................. 132 dev_ctl_clkmux ............................................................ 170, 180 dev_ctl_clkmux0 .................................................................. 180 dev_ctl_clkmux1 .................................................................. 180 dev_ctl_clkmux2 .................................................................. 180 dev_ctl_clkmux3 .................................................................. 180 dev_ctl_clkmux4 .................................................................. 180 dev_ctl_dmux ........................................................................ 182 dev_ctl_lpbk_s0 ..................................................................... 33 dev_ctl_rx_phdet_s0 ........................................................... 34 dev_ctl_tx_phdet_s0 ............................................................ 34 dev_dp_swrst_s0 ................................................................... 32 dev_dwfec_dat_swrst ........................................................ 32 dev_dwfec_mpu_swrst ........................................................ 32 dev_dwfec_pclk_pdn .................................................... 33, 170 dev_dwfec_rx_loc_inh ........................................................ 36 dev_dwfec_rx_lof_inh ........................................................ 36 dev_dwfec_rx_los_inh ........................................................ 36 dev_dwfec_rx_oof_inh ........................................................ 36 dev_dwfec_tx_loc_inh ........................................................ 36 dev_dwfec_tx_lof_inh ......................................................... 36 dev_dwfec_tx_los_inh ......................................................... 36 dev_dwfec_tx_oof_inh ........................................................ 36 dev_gpi_a0 ............................................................................... 178 dev_gpi_a1 ............................................................................... 178 dev_gpi_a2 ............................................................................... 178 dev_gpi_alarm ....................................................................... 174 dev_gpi_alarm0 ..................................................................... 178 dev_gpi_alarm1 ..................................................................... 178 dev_gpi_alarm2 ..................................................................... 178 dev_gpi_cfg0 .......................................................................... 177 dev_gpi_cfg1 .......................................................................... 177 dev_gpi_cfg2 .......................................................................... 177 dev_gpi_int_pol0 ................................................................... 177 dev_gpi_int_pol1 ................................................................... 177 dev_gpi_int_pol2 ................................................................... 177 dev_gpi_int_typ0 ................................................................... 177 dev_gpi_int_typ1 ................................................................... 177 dev_gpi_int_typ2 ................................................................... 177 dev_gpi_int_typ3 ................................................................... 177 dev_gpi_int_typ4 ................................................................... 177 dev_gpi_int_typ5 ................................................................... 177 dev_gpi_m0 ............................................................................... 178 dev_gpi_m1 ............................................................................... 178 dev_gpi_m2 ............................................................................... 178 dev_gpi_mask ......................................................................... 174 dev_gpi_mask0 ....................................................................... 178 dev_gpi_mask1 ........................................................................178 dev_gpi_mask2 ........................................................................178 dev_gpi_p0 ................................................................................178 dev_gpi_p1 ................................................................................178 dev_gpi_p2 ................................................................................178 dev_gpi_persist .....................................................................174 dev_gpi_persist0 ...................................................................178 dev_gpi_persist1 ...................................................................178 dev_gpi_persist2 ...................................................................178 dev_gpi_state .........................................................................174 dev_gpi_state0 .......................................................................178 dev_gpi_state1 .......................................................................178 dev_gpi_state2 .......................................................................178 dev_gpi0 ....................................................................................178 dev_gpi1 ....................................................................................178 dev_gpi2 ....................................................................................178 dev_gpio_cfg ..........................................................................174 dev_gpio_dir0 .........................................................................177 dev_gpio_dir1 .........................................................................177 dev_gpio_dir2 .........................................................................177 dev_gpo_sel ...........................................................................174 dev_gpo_sel0 .........................................................................177 dev_gpo_sel1 .........................................................................177 dev_gpo_sel2 .........................................................................178 dev_gpo_sel3 .........................................................................178 dev_gpo_val ...........................................................................174 dev_gpo_val0 .........................................................................177 dev_gpo_val1 .........................................................................177 dev_gpo_val2 .........................................................................177 dev_hold ..................................................................................171 dev_id0 .......................................................................................168 dev_id1 .......................................................................................168 dev_id2 .......................................................................................168 dev_id3 .......................................................................................168 dev_id4 .......................................................................................168 dev_loc_alarm_s0 ..................................................................31 dev_loc_line_rxclk ...................................................31, 36, 44 dev_loc_line_rxclk_m ..........................................................31 dev_loc_line_rxclk_p ...........................................................31 dev_loc_line_txclk ...................................................31, 36, 44 dev_loc_line_txclk_m ..........................................................31 dev_loc_line_txclk_p ...........................................................31 dev_loc_mask_s0 ....................................................................31 dev_loc_persist_s0 ...............................................................31 dev_loc_state_s0 ...................................................................31 dev_loc_sys_rxclk ..........................................................31, 36 dev_loc_sys_rxclk_m ...........................................................31 dev_loc_sys_rxclk_p ...........................................................31 dev_loc_sys_txclk ..........................................................31, 36 dev_loc_sys_txclk_m ...........................................................31 dev_loc_sys_txclk_p ............................................................31 dev_ltim_ref_sel ....................................................................35 dev_ltim_ref_sel_s0 ..............................................................35 dev_mpu_reg_swrst ..............................................................32 dev_mpureg_swrst ........................................................32, 173 dev_pdn_clkin_s0 ....................................................................33 dev_pdn_dwaco_s0 .................................................................33 dev_pdn_iclk .....................................................................33, 170 dev_pdn_in_s0 ...........................................................................33 dev_pdn_out_s0 .......................................................................33 dev_pdn_toaco_s0 ..................................................................33
194 194 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface list of objects (continued) object page object page dev_phdet_rx_pol .................................................................. 34 dev_phdet_rx_refdiv ............................................................ 34 dev_phdet_rx_refsel ........................................................... 34 dev_phdet_rx_vardiv ........................................................... 34 dev_phdet_rx_varsel ........................................................... 34 dev_phdet_tx_pol .................................................................. 34 dev_phdet_tx_refdiv ............................................................ 34 dev_phdet_tx_refsel ........................................................... 34 dev_phdet_tx_vardiv ............................................................ 34 dev_phdet_tx_varsel ........................................................... 34 dev_pm_trig_swrst ............................................................. 173 dev_pmclk_a ........................................................................... 173 dev_pmclk_alarm ................................................................. 173 dev_pmclk_cfg ...................................................................... 173 dev_pmclk_ioctl ................................................................... 173 dev_pmclk_m ........................................................................... 173 dev_pmclk_mask ................................................................... 173 dev_pmclk_preld .................................................................. 173 dev_pmmode ............................................................................ 173 dev_rclkli_pdn ........................................................................ 33 dev_rclksi_pdn ....................................................................... 33 dev_rclkso_pdn ...................................................................... 33 dev_rdli_pdn ............................................................................ 33 dev_rdso_pdn .......................................................................... 33 dev_rdw_cs_pdn ..................................................................... 33 dev_rdw_dato_pdn ................................................................ 33 dev_rdw2tdw_lb ..................................................................... 33 dev_rsys2tsys_lb .................................................................. 33 dev_rtoac_cs_pdn ................................................................. 33 dev_rtoac_dat_pdn ............................................................... 33 dev_rx_alrmstat_inh_s0 ..................................................... 36 dev_scratch ........................................................................... 168 dev_sonfec_dat_swrst ....................................................... 32 dev_sonfec_mpu_swrst ...................................................... 32 dev_sonfec_pclk_pdn .................................................. 33, 170 dev_sonfec_rx_loc_inh ...................................................... 36 dev_sonfec_rx_lof_inh ....................................................... 36 dev_sonfec_rx_los_inh ....................................................... 36 dev_sonfec_rx_oof_inh ...................................................... 36 dev_sonfec_tx_loc_inh ....................................................... 36 dev_sonfec_tx_lof_inh ....................................................... 36 dev_sonfec_tx_los_inh ....................................................... 36 dev_sonfec_tx_oof_inh ...................................................... 36 dev_tclkli_pdn ........................................................................ 33 dev_tclklo_pdn ...................................................................... 33 dev_tclksi_pdn ........................................................................ 33 dev_tdlo_pdn ........................................................................... 33 dev_tdsi_pdn ............................................................................ 33 dev_tdw_cs_pdn ..................................................................... 33 dev_tdw2rdw_lb ..................................................................... 33 dev_tfrmli_pdn ....................................................................... 33 dev_tline2rline_lb ................................................................. 33 dev_trsen2rrsde_lb ............................................................. 33 dev_ttoac_pdn ........................................................................ 33 dev_tx_alrmstat_inh_s0 ...................................................... 36 dev_ver ..................................................................................... 168 ds_n ............................................................................................ 170 dw_alarm_s0 ..................................... 73, 75, 95, 96, 98, 100, 102 dw_alarm_v2_s0 .......................................... 71, 81, 99, 103, 105 dw_dwac_rx_ctl_s0 ............................................................ 106 dw_dwac_rx_ctl_v2_s0 ...................................................... 106 dw_dwac_tx_ctl_s0 ............................................................... 80 dw_es_rxdata .................................................................... 61, 94 dw_es_rxsync ......................................................................... 61 dw_mask_s0 ...................................... 73, 75, 95, 96, 98, 100, 102 dw_mask_v2_s0 ............................................ 71, 81, 99, 103, 105 dw_persist_2_s0 ................................... 70, 73, 75, 98, 100, 102 dw_persist_v2_s0 ....................................... 71, 81, 99, 103, 105 dw_prbs_alarm_s0 .............................................................. 110 dw_prbs_ctl_s0 .............................................................. 80, 110 dw_prbs_ctl_v2_s0 ........................................................ 81, 111 dw_prbs_mask_s0 ................................................................. 110 dw_prbs_persist_s0 ........................................................... 110 dw_prbs_state_s0 ............................................................... 110 dw_rs_txdata .......................................................................... 94 dw_rx_bei2_bit_blk .............................................................. 104 dw_rx_bei2_disable ............................................................. 104 dw_rx_bii1_stat .............................................................. 49, 103 dw_rx_bii1_stat_new_a ................................................ 49, 103 dw_rx_bii1_stat_new_m ..................................................... 103 dw_rx_bii1_stat_new_p ...................................................... 103 dw_rx_bii2_stat .............................................................. 50, 105 dw_rx_bii2_stat_new_a ................................................ 50, 105 dw_rx_bii2_stat_new_m ..................................................... 105 dw_rx_bii2_stat_new_p ...................................................... 105 dw_rx_bip2_bit_blk .............................................................. 104 dw_rx_bip2_disable ............................................................. 104 dw_rx_cnt_bei00 ................................................................... 174 dw_rx_cnt_bei00_s0 .............................................................. 98 dw_rx_cnt_bei01 ................................................................... 174 dw_rx_cnt_bei01_s0 .............................................................. 98 dw_rx_cnt_bei10 ................................................................... 174 dw_rx_cnt_bei10_s0 ............................................................ 100 dw_rx_cnt_bei11 ................................................................... 174 dw_rx_cnt_bei11_s0 ............................................................ 100 dw_rx_cnt_bei20_v2_s0 ...................................................... 104 dw_rx_cnt_bei21_v2_s0 ...................................................... 104 dw_rx_cnt_bip00 ................................................................... 174 dw_rx_cnt_bip00_s0 .............................................................. 97 dw_rx_cnt_bip01 ................................................................... 174 dw_rx_cnt_bip01_s0 .............................................................. 97 dw_rx_cnt_bip10 ................................................................... 174 dw_rx_cnt_bip10_s0 .............................................................. 99 dw_rx_cnt_bip11 ................................................................... 174 dw_rx_cnt_bip11_s0 .............................................................. 99 dw_rx_cnt_bip20_v2_s0 ...................................................... 104 dw_rx_cnt_bip21_v2_s0 ...................................................... 104 dw_rx_cnt_prbs ................................................................... 170 dw_rx_cnt_prbs_s0 ............................................................ 110 dw_rx_ctl_ais_2_s0 ..................................................... 102, 103 dw_rx_ctl_ais_v2_s0 ................................................... 108, 109 dw_rx_ctl_aisbyte_s0 ........................................................ 102 dw_rx_ctl_bii_s0 ............................................................ 98, 100 dw_rx_ctl_bii2_v2_2_s0 ...................................................... 104 dw_rx_ctl_biicntd_s0 .................................................. 98, 100 dw_rx_ctl_bip_s0 ............................................................. 97, 99 dw_rx_ctl_cntd_v2_s0 ...................................................... 105 dw_rx_ctl_oh_v2_s0 ........................................... 103, 108, 109 dw_rx_ctl_oh0_2_s0 ............................................................. 95 dw_rx_ctl_oh1_2_s0 ............................................................. 95 dw_rx_ctl_oh2_2_s0 ............................................................. 96 dw_rx_ctl_oh3_2_s0 ............................................................. 96 dw_rx_ctl_top_s0 ............................... 95, 97, 98, 99, 100, 108 dw_rx_ctl_v2_s0 ............................................ 99, 104, 108, 111
agere systems inc. 195 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface list of objects (continued) object page object page dw_rx_mon_v2_s0 ......................................................... 103, 105 dw_rx_no_fs .......................................................................... 111 dw_rx_val_oh01_s0 ................................................................ 95 dw_rx_val_oh23_s0 .......................................................... 95, 96 dw_rxais_apsinh ....................................................... 49, 50, 109 dw_rxais_clrcntd ......................................................... 49, 103 dw_rxais_cond .................................................... 47, 66, 76, 107 dw_rxais_det ............................................. 49, 50, 102, 103, 107 dw_rxais_det_a ..................................................................... 102 dw_rxais_det_m .................................................................... 102 dw_rxais_det_p ..................................................................... 102 dw_rxais_detinh ..................................................... 49, 107, 108 dw_rxais_frm ................................................................... 49, 103 dw_rxais_ftflinh ................................................ 49, 50, 77, 108 dw_rxais_gccinh ................................................ 49, 50, 77, 109 dw_rxais_ins ............................................................ 49, 107, 108 dw_rxais_row .................................................................. 49, 103 dw_rxais_setcntd ......................................................... 49, 102 dw_rxais_tcminh ...................................................... 49, 50, 109 dw_rxais_tcmstat_iaeinh ................................................. 109 dw_rxbdi0_cntd ................................................................ 48, 98 dw_rxbdi0_det ................................................................... 48, 98 dw_rxbdi0_det_a ..................................................................... 98 dw_rxbdi0_det_m .................................................................... 98 dw_rxbdi0_det_p ..................................................................... 98 dw_rxbdi1_cntd .............................................................. 49, 100 dw_rxbdi1_det ................................................................. 49, 100 dw_rxbdi1_det_a ................................................................... 100 dw_rxbdi1_det_m .................................................................. 100 dw_rxbdi1_det_p ................................................................... 100 dw_rxbdi2_cntd .............................................................. 50, 105 dw_rxbdi2_det ................................................................. 50, 105 dw_rxbdi2_det_a ................................................................... 105 dw_rxbdi2_det_m .................................................................. 105 dw_rxbdi2_det_p ................................................................... 105 dw_rxbei0_bit_blk .................................................................. 98 dw_rxbei0_disable ................................................................. 98 dw_rxbei00_ecnt ..................................................................... 98 dw_rxbei01_ecnt ............................................................... 48, 98 dw_rxbei1_bit_blk ................................................................ 100 dw_rxbei1_disable ............................................................... 100 dw_rxbei10_ecnt ................................................................... 100 dw_rxbei11_ecnt ............................................................. 49, 100 dw_rxbei20_ecnt ................................................................... 104 dw_rxbei21_ecnt ............................................................. 50, 104 dw_rxbii0_frm .......................................................................... 98 dw_rxbii0_row ......................................................................... 98 dw_rxbii1_frm ........................................................................ 100 dw_rxbii1_row ....................................................................... 100 dw_rxbii1_stat_cntd ..................................................... 49, 103 dw_rxbii2_frm ........................................................................ 104 dw_rxbii2_row ....................................................................... 104 dw_rxbii2_stat_cntd ..................................................... 50, 105 dw_rxbip0_bit_blk .................................................................. 97 dw_rxbip0_disable ................................................................. 97 dw_rxbip0_frm ......................................................................... 97 dw_rxbip0_row ........................................................................ 97 dw_rxbip00_ecnt ..................................................................... 97 dw_rxbip01_ecnt ............................................................... 48, 97 dw_rxbip1_bit_blk .................................................................. 99 dw_rxbip1_disable ................................................................. 99 dw_rxbip1_frm .........................................................................99 dw_rxbip1_row ........................................................................99 dw_rxbip10_ecnt .....................................................................99 dw_rxbip11_ecnt ...............................................................49, 99 dw_rxbip2_frm .......................................................................104 dw_rxbip2_row ......................................................................104 dw_rxbip20_ecnt ...................................................................104 dw_rxbip21_ecnt .............................................................50, 104 dw_rxfix_cond .....................................................47, 66, 76, 107 dw_rxfix_det ..............................................49, 50, 102, 103, 107 dw_rxfix_det_a ......................................................................102 dw_rxfix_det_m .....................................................................102 dw_rxfix_det_p ......................................................................102 dw_rxfix_detinh ............................................................107, 108 dw_rxfix_ins ...................................................................107, 108 dw_rxfix_val ............................................................49, 102, 107 dw_rxiae0_cntd .................................................................48, 99 dw_rxiae0_det ..............................................................44, 48, 99 dw_rxiae0_det_a .....................................................................99 dw_rxiae0_det_m .....................................................................99 dw_rxiae0_det_p .....................................................................99 dw_rxlck_fix ..........................................................................108 dw_rxloc_aisinh .....................................................49, 107, 108 dw_rxlof_aisinh ......................................................49, 107, 108 dw_rxlos_aisinh ......................................................49, 107, 108 dw_rxoa12_mfas ..............................................................48, 108 dw_rxoci_cond ....................................................47, 66, 76, 107 dw_rxoci_det .......................................44, 49, 50, 102, 103, 107 dw_rxoci_det_a .....................................................................102 dw_rxoci_det_m ....................................................................102 dw_rxoci_det_p .....................................................................102 dw_rxoci_detinh .....................................................49, 107, 108 dw_rxoci_ins ............................................................49, 107, 108 dw_rxoh0_cntd .......................................................................95 dw_rxoh0_det_a ......................................................................95 dw_rxoh0_det_m .....................................................................95 dw_rxoh0_frm ..........................................................................95 dw_rxoh0_row .........................................................................95 dw_rxoh0_val ...........................................................................95 dw_rxoh0123_grp ............................................48, 49, 50, 94, 95 dw_rxoh1_cntd .......................................................................95 dw_rxoh1_det_a ......................................................................95 dw_rxoh1_det_m .....................................................................95 dw_rxoh1_frm ..........................................................................95 dw_rxoh1_row .........................................................................95 dw_rxoh1_val ...........................................................................95 dw_rxoh2_cntd .......................................................................96 dw_rxoh2_det_a ......................................................................95 dw_rxoh2_det_m .....................................................................95 dw_rxoh2_frm ..........................................................................96 dw_rxoh2_row .........................................................................96 dw_rxoh2_val ...........................................................................95 dw_rxoh3_cntd .......................................................................96 dw_rxoh3_det_a ......................................................................96 dw_rxoh3_det_m .....................................................................96 dw_rxoh3_frm ..........................................................................96 dw_rxoh3_row .........................................................................96 dw_rxoh3_val ...........................................................................96 dw_rxoof_aisinh .....................................................49, 107, 108 dw_rxprbs_29_31_pat ..........................................................110 dw_rxprbs_ecnt ...................................................................110
196 196 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface list of objects (continued) object page object page dw_rxprbs_ins ....................................................................... 111 dw_rxprbs_ins_1berrins ................................................... 111 dw_rxprbs_ins_29_31_pat .................................................. 111 dw_rxprbs_ins_inv ............................................................... 111 dw_rxprbs_inv ....................................................................... 110 dw_rxprbs_sync ................................................................... 110 dw_rxprbs_sync_a .............................................................. 110 dw_rxprbs_sync_m .............................................................. 110 dw_rxprbs_sync_p .............................................................. 110 dw_rxprbsdata ..................................................................... 110 dw_rxprbsdata_en .............................................................. 110 dw_rxsd_aisinh ....................................................... 49, 107, 108 dw_rxsf_aisinh ........................................................ 49, 107, 108 dw_state_2_s0 ....................................... 70, 73, 75, 98, 100, 102 dw_state_v2_s0 ................................................... 71, 81, 99, 105 dw_tx_cbpass .......................................................................... 82 dw_tx_cnt_prbs_v2_s0 ......................................................... 81 dw_tx_ctl_ais_2_s0 ................................................................ 78 dw_tx_ctl_ais_v2_s0 ............................................................. 78 dw_tx_ctl_bdi0inh_2_s0 ....................................................... 70 dw_tx_ctl_bdi1inh_v2_s0 ..................................................... 73 dw_tx_ctl_bdi2inh_v2_s0 ..................................................... 75 dw_tx_ctl_bii_s0 ............................................................... 69, 72 dw_tx_ctl_bii_v2_s0 ............................................................... 74 dw_tx_ctl_bip_s0 .............................................................. 69, 72 dw_tx_ctl_bip_v2_s0 ............................................................. 74 dw_tx_ctl_oa12_pat_s0 ................................................. 62, 78 dw_tx_ctl_oa12_s0 ................................................................ 62 dw_tx_ctl_oh0_2_s0 .............................................................. 64 dw_tx_ctl_oh1_2_s0 .............................................................. 64 dw_tx_ctl_oh2_2_s0 .............................................................. 64 dw_tx_ctl_oh3_2_s0 .............................................................. 64 dw_tx_ctl_top_2_s0 ................................ 61, 62, 64, 78, 80, 82 dw_tx_ctl_top_v2_s0 .............................. 62, 71, 74, 76, 78, 82 dw_tx_es_frm .......................................................................... 61 dw_tx_no_fs ............................................................................. 82 dw_tx_passthru ..................................................................... 61 dw_txais_apsinh .......................................................... 47, 77, 78 dw_txais_ftflinh .............................................................. 47, 78 dw_txais_gccinh ............................................................... 47, 78 dw_txais_ins ....................................................................... 47, 78 dw_txais_tcminh ......................................................... 47, 77, 78 dw_txais_tcmstat_iaeinh .............................................. 68, 78 dw_txais_tcmstat_iaeinh0 .................................................. 44 dw_txbdi_aisinh ....................................................................... 66 dw_txbdi_det .................................................................... 66, 106 dw_txbdi_fixinh ....................................................................... 66 dw_txbdi_ins ............................................................................. 66 dw_txbdi_locinh ..................................................................... 66 dw_txbdi_lofinh ...................................................................... 66 dw_txbdi_losinh ..................................................................... 66 dw_txbdi_ociinh ...................................................................... 66 dw_txbdi_oofinh ..................................................................... 66 dw_txbdi_sdinh ........................................................................ 66 dw_txbdi_sfinh ........................................................................ 66 dw_txbdi_timerinh ................................................................. 66 dw_txbdi0_aisinh ..................................................................... 70 dw_txbdi0_det ........................................................ 46, 48, 67, 70 dw_txbdi0_det_a ..................................................................... 70 dw_txbdi0_det_m ..................................................................... 70 dw_txbdi0_det_p ..................................................................... 70 dw_txbdi0_fixinh ..................................................................... 70 dw_txbdi0_inh .................................................................... 67, 70 dw_txbdi0_ins .............................................................. 66, 67, 70 dw_txbdi0_locinh ................................................................... 70 dw_txbdi0_lofinh ................................................................... 70 dw_txbdi0_losinh ................................................................... 70 dw_txbdi0_ociinh .................................................................... 70 dw_txbdi0_oofinh .................................................................. 70 dw_txbdi0_sdinh ..................................................................... 70 dw_txbdi0_sfinh ...................................................................... 70 dw_txbdi0_timerinh ............................................................... 70 dw_txbdi1_aisinh .................................................................... 73 dw_txbdi1_det ............................................................. 47, 49, 73 dw_txbdi1_det_a ..................................................................... 73 dw_txbdi1_det_m .................................................................... 73 dw_txbdi1_det_p ..................................................................... 73 dw_txbdi1_fixinh ..................................................................... 73 dw_txbdi1_inh .......................................................................... 73 dw_txbdi1_ins .................................................................... 66, 73 dw_txbdi1_locinh ................................................................... 73 dw_txbdi1_lofinh ................................................................... 73 dw_txbdi1_losinh ................................................................... 73 dw_txbdi1_ociinh .................................................................... 73 dw_txbdi1_oofinh .................................................................. 73 dw_txbdi1_sdinh ..................................................................... 73 dw_txbdi1_sfinh ...................................................................... 73 dw_txbdi1_timerinh ............................................................... 73 dw_txbdi2_aisinh .................................................................... 75 dw_txbdi2_det ............................................................. 47, 50, 75 dw_txbdi2_det_a ..................................................................... 75 dw_txbdi2_det_m .................................................................... 75 dw_txbdi2_det_p ..................................................................... 75 dw_txbdi2_fixinh ..................................................................... 75 dw_txbdi2_inh .......................................................................... 75 dw_txbdi2_ins .................................................................... 66, 75 dw_txbdi2_locinh ................................................................... 75 dw_txbdi2_lofinh ................................................................... 75 dw_txbdi2_losinh ................................................................... 75 dw_txbdi2_ociinh .................................................................... 75 dw_txbdi2_oofinh .................................................................. 75 dw_txbdi2_sdinh ..................................................................... 75 dw_txbdi2_sfinh ...................................................................... 75 dw_txbdi2_timerinh ............................................................... 75 dw_txbei0_errins ................................................................... 69 dw_txbei0_ins .......................................................................... 69 dw_txbei1_errins ................................................................... 72 dw_txbei1_ins .......................................................................... 72 dw_txbei2_errins ................................................................... 74 dw_txbei2_ins .......................................................................... 74 dw_txbii0_frm .......................................................................... 69 dw_txbii0_row ......................................................................... 69 dw_txbii1_frm .......................................................................... 72 dw_txbii1_row ......................................................................... 72 dw_txbii1_stat_ins ........................................................... 47, 74 dw_txbii2_frm .......................................................................... 74 dw_txbii2_row ......................................................................... 74 dw_txbii2_stat_ins ........................................................... 47, 76 dw_txbip0_errins ................................................................... 69 dw_txbip0_frm ......................................................................... 69 dw_txbip0_ins .................................................................... 68, 69 dw_txbip0_row ........................................................................ 69 dw_txbip1_errins ................................................................... 72 dw_txbip1_frm ......................................................................... 72
agere systems inc. 197 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface list of objects (continued) object page object page dw_txbip1_ins ........................................................................... 72 dw_txbip1_row ........................................................................ 72 dw_txbip2_errins ................................................................... 74 dw_txbip2_frm ......................................................................... 74 dw_txbip2_ins ........................................................................... 74 dw_txbip2_row ........................................................................ 74 dw_txdefault .......................................................................... 62 dw_txfix_ins ....................................................................... 47, 78 dw_txfix_val ...................................................................... 47, 78 dw_txiae_det ............................................................................ 67 dw_txiae_ins ............................................................................. 67 dw_txiae_lofinh ...................................................................... 67 dw_txiae_oofinh ..................................................................... 67 dw_txiae0_det ........................................................ 46, 48, 68, 71 dw_txiae0_det_a ..................................................................... 71 dw_txiae0_det_m ..................................................................... 71 dw_txiae0_det_p ..................................................................... 71 dw_txiae0_inh ............................................................... 46, 67, 71 dw_txiae0_ins ..................................................................... 46, 71 dw_txiae0_lofinh .............................................................. 46, 71 dw_txiae0_oofinh ............................................................. 46, 71 dw_txlck_fix ...................................................................... 47, 78 dw_txloc_aisinh ......................................................... 47, 76, 78 dw_txlof_aisinh .......................................................... 47, 76, 78 dw_txlos_aisinh ......................................................... 47, 76, 78 dw_txmfas_ins ................................................................... 46, 62 dw_txmfas_sync ..................................................................... 62 dw_txoa1_val ..................................................................... 46, 62 dw_txoa12_ins ................................................................... 46, 62 dw_txoa12_mfas ................................................... 46, 47, 77, 78 dw_txoa12_pair ....................................................................... 77 dw_txoa12_pairs ............................................................... 46, 62 dw_txoa2_val ..................................................................... 46, 62 dw_txoci_ins ...................................................................... 47, 78 dw_txoh0_frm ......................................................................... 64 dw_txoh0_ins ........................................................................... 64 dw_txoh0_row ........................................................................ 64 dw_txoh0_val .......................................................................... 64 dw_txoh1_frm ......................................................................... 64 dw_txoh1_ins ........................................................................... 64 dw_txoh1_row ........................................................................ 64 dw_txoh1_val .......................................................................... 64 dw_txoh2_frm ......................................................................... 64 dw_txoh2_ins ........................................................................... 64 dw_txoh2_row ........................................................................ 64 dw_txoh2_val .......................................................................... 64 dw_txoh3_frm ......................................................................... 64 dw_txoh3_ins ........................................................................... 64 dw_txoh3_row ........................................................................ 64 dw_txoh3_val .......................................................................... 64 dw_txoof_aisinh ......................................................... 47, 76, 78 dw_txprbs_1berrins ............................................................. 80 dw_txprbs_29_31_pat ............................................................ 80 dw_txprbs_ecnt ..................................................................... 81 dw_txprbs_ins ......................................................................... 80 dw_txprbs_inv ......................................................................... 80 dw_txprbs_mon_29_31_pat ................................................. 81 dw_txprbs_mon_inv .............................................................. 81 dw_txprbs_sync ..................................................................... 81 dw_txprbs_sync_a ................................................................ 81 dw_txprbs_sync_m ................................................................ 81 dw_txprbs_sync_p .................................................................81 dw_txrxcond_aisinh ..................................................47, 76, 78 dw_txrxcond_fixinh ..................................................47, 76, 78 dw_txrxcond_ociinh .................................................47, 76, 78 dwac_dw_txdata_en ..............................................................79 dwac_rxbdi0_ovwr .........................................................48, 106 dwac_rxbdi1_ovwr .........................................................49, 106 dwac_rxbdi2_ovwr .........................................................50, 106 dwac_rxbei0_ovwr .........................................................48, 106 dwac_rxbei1_ovwr .........................................................49, 106 dwac_rxbei2_ovwr .........................................................50, 106 dwac_rxiae0_ovwr .........................................................48, 106 dwac_txins ................................................................................80 dwfec_mode0 ............................................................................41 dwfec_mode1_s0 .....................................................................41 dwfec_mux_s0 ..........................................................................61 dwfec_rst_mon .......................................................................32 dwfec_rx_10g_2g5 ............................................................40, 41 dwfec_rx_16_64 ..................................................................40, 41 dwfec_rx_fec_dw ............................................................40, 41 dwfec_rx_rst_mon_s0 ..........................................................32 dwfec_rx_rst_mon_s1 ..........................................................32 dwfec_rx_rst_mon_s2 ..........................................................32 dwfec_rx_rst_mon_s3 ..........................................................32 dwfec_rx78clk .........................................................................30 dwfec_rx83data ......................................................................30 dwfec_rxdatao .......................................................................30 dwfec_sys_rx83data .............................................................94 dwfec_tx_10g_2g5 ............................................................40, 41 dwfec_tx_16_64 ..................................................................40, 41 dwfec_tx_dmux .......................................................................30 dwfec_tx_fec_dw .............................................................40, 41 dwfec_tx_rst_mon_s0 ..........................................................32 dwfec_tx_rst_mon_s1 ..........................................................32 dwfec_tx_rst_mon_s2 ..........................................................32 dwfec_tx_rst_mon_s3 ..........................................................32 dwfec_tx78clk .........................................................................30 dwfec_txdatai .........................................................................30 dwfec_txdatao ........................................................................30 e es_alarm_s0 ......................................................................54, 112 es_ctl_s0 ............................................................................54, 112 es_dw_txdata ...........................................................................61 es_mask_s0 ........................................................................54, 112 es_rx_overflw_a ............................................................44, 112 es_rx_overflw_m .................................................................112 es_rx_restart .......................................................................112 es_rx_undrflw_a ............................................................44, 112 es_rx_undrflw_m .................................................................112 es_tx_overflw_a ..............................................................44, 54 es_tx_overflw_m ....................................................................54 es_tx_restart ..........................................................................54 es_tx_undrflw_a ..............................................................44, 54 es_tx_undrflw_m ...................................................................54 f fifo_max ....................................................................................131
198 198 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface list of objects (continued) object page object page fifo_min ..................................................................................... 131 frm_alarm_s0 ............................................. 55, 59, 60, 86, 87, 88 frm_dis ........................................................................................ 56 frm_dw_rx_lof ...................................................................... 107 frm_dw_rx_oof ..................................................................... 107 frm_dw_rxlos ....................................................................... 107 frm_dw_txdata ....................................................................... 61 frm_dw_txlof .......................................................................... 76 frm_dw_txlos .......................................................................... 76 frm_dw_txoof ......................................................................... 76 frm_mask_s0 ............................................... 55, 59, 60, 86, 87, 88 frm_persist_s0 .......................................... 55, 59, 60, 86, 87, 88 frm_rx_ctl_lof_2_s0 ...................................................... 60, 88 frm_rx_ctl_losdet_s0 ......................................................... 86 frm_rx_ctl_oa12_pat_3_s0 ................................................. 87 frm_rx_ctl_oa12_s0 .............................................................. 87 frm_rx_ctl_oof_3_s0 ............................................................ 87 frm_rx_disable ....................................................................... 87 frm_rxlof .................................................. 36, 44, 66, 67, 88, 108 frm_rxlof_a ............................................................................. 88 frm_rxlof_clr ........................................................................ 88 frm_rxlof_m ............................................................................. 88 frm_rxlof_p ............................................................................. 88 frm_rxlof_set ......................................................................... 88 frm_rxlos ....................................................... 36, 44, 66, 86, 108 frm_rxlos_a ............................................................................. 86 frm_rxlos_det ........................................................................ 86 frm_rxlos_m ............................................................................ 86 frm_rxlos_p ............................................................................. 86 frm_rxoa1_val ......................................................................... 87 frm_rxoa12_pairclr .............................................................. 87 frm_rxoa12_pairs ................................................................... 87 frm_rxoa12_pairset .............................................................. 87 frm_rxoa2_val ......................................................................... 87 frm_rxoof ................................................. 36, 44, 66, 67, 87, 108 frm_rxoof_a ............................................................................ 87 frm_rxoof_clr ........................................................................ 87 frm_rxoof_m ............................................................................ 87 frm_rxoof_p ............................................................................ 87 frm_rxoof_set ........................................................................ 87 frm_state_s0 .............................................. 55, 59, 60, 86, 87, 88 frm_tx_ctl_losdet ................................................................ 55 frm_tx_ctl_losdet_s0 ......................................................... 55 frm_tx_ctl_oa12_pat_3_s0 .................................................. 59 frm_tx_ctl_oa12_s0 ............................................................... 59 frm_tx_ctl_oof_3_s0 ............................................................ 59 frm_tx_disable ........................................................................ 59 frm_txlof ................................................................ 36, 44, 60, 78 frm_txlof_a .............................................................................. 60 frm_txlof_clr ......................................................................... 60 frm_txlof_m ............................................................................. 60 frm_txlof_p .............................................................................. 60 frm_txlof_set ......................................................................... 60 frm_txlos ................................................................ 36, 44, 55, 78 frm_txlos_a ............................................................................. 55 frm_txlos_det ......................................................................... 55 frm_txlos_m ............................................................................. 55 frm_txlos_p ............................................................................. 55 frm_txoa1_val ......................................................................... 59 frm_txoa12_pairclr .............................................................. 59 frm_txoa12_pairs ................................................................... 59 frm_txoa12_pairset .............................................................. 59 frm_txoa2_val ........................................................................ 59 frm_txoof ............................................................... 36, 44, 59, 78 frm_txoof_a ............................................................................ 59 frm_txoof_clr ........................................................................ 59 frm_txoof_m ............................................................................ 59 frm_txoof_p ............................................................................ 59 frm_txoof_set ........................................................................ 59 g glbl_resync ........................................................................... 131 i inth_n ................................................................................ 169, 170 intl_n ................................................................................ 169, 170 l line_rx_dwfec_clkmux ........................................................ 30 line_rx83clk ............................................................................. 30 line_rx83loc ............................................................ 66, 107, 108 line_rxdatai ............................................................................. 30 line_tx_dmux ............................................................................ 30 line_tx_dwfec_clkmux ........................................................ 30 line_tx_hs_clkmux ................................................................ 30 line_tx_hsclk .......................................................................... 30 line_tx_ls_clkmux ................................................................. 30 line_tx_lsclk ........................................................................... 30 line_tx83clk ............................................................................. 30 line_tx83loc ....................................................................... 76, 78 line_txdatao ............................................................................ 30 m mpdb_8_16 .................................................................. 20, 167, 171 mpmode_as ...................................................................... 167, 168 mpparen ................................................................................... 171 mptype_im .................................................................. 20, 167, 168 mpu_dw_frm_oa1_val ........................................................... 56 mpu_dw_frm_oa12_pairclr ................................................ 56 mpu_dw_frm_oa12_pairs ..................................................... 56 mpu_dw_frm_oa12_pairset ................................................. 56 mpu_dw_frm_oa2_val ........................................................... 56 mpu_dw_frm_oof_clr .......................................................... 56 mpu_dw_frm_oof_set .......................................................... 56 mpu_dw_r2t_lb ........................................................................ 61 mpu_sonfec_tx_10g_2g5 .................................................... 131 o oh_alarm_rxl ............................................................... 48, 49, 50 oh_rxl ............................................................................. 48, 49, 50 oh_txl ................................................................................... 46, 47 ohp_rx_ais_rdi ...................................................................... 116 ohp_rx_aisd_dis .................................................................... 134 ohp_rx_b1cal_dis ................................................................. 166 ohp_rx_b1corrupt_s0 ........................................................ 166 ohp_rx_b1mon_dis ............................................................... 132 ohp_rx_b2cal_dis ................................................................. 164 ohp_rx_b2corrupt_s0 ........................................................ 164
agere systems inc. 199 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface list of objects (continued) object page object page ohp_rx_cvs_pm ...................................................................... 174 ohp_rx_cvs_pm_s0 ............................................................... 132 ohp_rx_descr_dis ................................................................ 132 ohp_rx_f1s1byte_s0 .................................................... 144, 147 ohp_rx_f1s1det_s0 ...................................................... 144, 147 ohp_rx_frm_dis ..................................................................... 130 ohp_rx_j0exp0_s0 ................................................................. 142 ohp_rx_j0exp31_s0 ............................................................... 142 ohp_rx_j0sus0_s0 ................................................................. 142 ohp_rx_j0sus31_s0 ............................................................... 142 ohp_rx_k1k2byte_s0 ............................................................ 146 ohp_rx_los_s0 ....................................................................... 130 ohp_rx_maint_s0 ................................................... 138, 139, 142 ohp_rx_nsa_0_alarm_s0 ............................ 130, 142, 146, 163 ohp_rx_nsa_0_mask_s0 .............................. 130, 142, 146, 163 ohp_rx_nsa_0_persist_s0 ......................... 130, 142, 146, 163 ohp_rx_nsa_0_state_s0 ............................. 130, 142, 146, 163 ohp_rx_nsa_1_alarm_s0 ............................ 142, 144, 146, 147 ohp_rx_nsa_1_mask_s0 .............................. 142, 144, 146, 147 ohp_rx_pm ............................................................................... 174 ohp_rx_pm_s0 ......................................................... 130, 134, 146 ohp_rx_post_b2mon_dis .................................................... 135 ohp_rx_post_cvl_l_pm ...................................................... 174 ohp_rx_post_cvl_l_pm_s0 ................................................ 135 ohp_rx_post_cvl_u_pm ...................................................... 174 ohp_rx_post_cvl_u_pm_s0 ............................................... 135 ohp_rx_prbs_ber ................................................................. 170 ohp_rx_prbs_ber_s0 ........................................................... 163 ohp_rx_pre_b2mon_dis ...................................................... 135 ohp_rx_pre_cvl_l_pm ......................................................... 174 ohp_rx_pre_cvl_l_pm_s0 .................................................. 135 ohp_rx_pre_cvl_u_pm ........................................................ 174 ohp_rx_pre_cvl_u_pm_s0 .................................................. 135 ohp_rx_prov_s0 ... 130, 132, 139, 140, 141, 146, 162, 163, 164, 166 ohp_rx_rei_l_pm ................................................................... 174 ohp_rx_rei_l_pm_s0 ............................................................. 148 ohp_rx_rei_u_pm .................................................................. 174 ohp_rx_rei_u_pm_s0 ............................................................ 148 ohp_rx_sa_alarm_s0 ........................................... 130, 134, 138 ohp_rx_sa_mask_s0 ............................................. 130, 134, 138 ohp_rx_sa_persist_s0 ........................................ 130, 134, 138 ohp_rx_sa_state_s0 ............................................ 130, 134, 138 ohp_rx_scrm_dis .................................................................. 165 ohp_rx_sdsf_clr4 ................................................................ 138 ohp_rx_sdsf_dt3 .................................................................. 138 ohp_rx_sdsf_set3 ................................................................ 138 ohp_tx_ais_rdi ............................................................... 115, 117 ohp_tx_ais_rdi_s0 ................................................................ 158 ohp_tx_b2_bypass ................................................................ 155 ohp_tx_b2mon_dis ................................................................ 135 ohp_tx_cvl_l_pm .................................................................. 174 ohp_tx_cvl_l_pm_s0 ............................................................ 135 ohp_tx_cvl_u_pm .................................................................. 174 ohp_tx_cvs_pm ...................................................................... 174 ohp_tx_f1s1byte_s0 .................................................... 154, 158 ohp_tx_j0byte0_s0 ............................................................... 153 ohp_tx_j0byte31_s0 ............................................................. 153 ohp_tx_k1k2 ............................................................................ 117 ohp_tx_k1k2byte_s0 ............................................................ 158 ohp_tx_loh_proc_dis ................................. 150, 151, 158, 159 ohp_tx_m1corrupt_s0 ........................................................159 ohp_tx_maint ..........................................................................117 ohp_tx_maint_s0 ....................150, 152, 153, 154, 157, 158, 159 ohp_tx_nsa_alarm_s0 .........................................................134 ohp_tx_nsa_mask_s0 ...........................................................134 ohp_tx_nsa_persist_s0 ......................................................134 ohp_tx_nsa_state_s0 ..........................................................134 ohp_tx_pm ................................................................................174 ohp_tx_pm_s0 ..........................................................................134 ohp_tx_prov_s0 .............................150, 151, 152, 159, 162, 164 ohp_tx_soh_proc_dis .........................150, 152, 153, 154, 155 otuk_ais_rxl ..............................................................................50 otuk_ais_txl ...............................................................................47 otuk_iae_txl .........................................................................46, 47 otuk_lck_rxl .............................................................................50 otuk_oci_rxl ..............................................................................50 otuk_sf ........................................................................................45 otuk_sf_txl ..........................................................................46, 47 p parity .........................................................................................169 pm_clk .......................................................................................173 pump_dn ......................................................................................34 pump_up ......................................................................................34 r r2tf_lb ......................................................................................185 rclkli ...........................................................................................34 rclksi ...........................................................................................34 rdw2tdw_lb .......................................................................61, 185 ref_clk .......................................................................................34 ref_phs .......................................................................................34 res2tes_lb ...............................................................................185 rs_alarm_s0 ........................................................................84, 93 rs_ber_sd ................................................................................107 rs_ber_sf .................................................................................107 rs_err_bitblk ...........................................................................90 rs_mask_2_s0 ......................................................................84, 93 rs_persist_s0 ...........................................................................93 rs_rx_cnt_0to1_errbit0_s0 ................................................90 rs_rx_cnt_0to1_errbit1_s0 ................................................90 rs_rx_cnt_1to0_errbit0_s0 ................................................90 rs_rx_cnt_1to0_errbit1_s0 ................................................90 rs_rx_cnt_berrep_s0 ...........................................................93 rs_rx_cnt_errbit0_s0 ...........................................................90 rs_rx_cnt_errbit1_s0 ...........................................................90 rs_rx_cnt_errblk0_s0 ..........................................................90 rs_rx_cnt_errblk1_s0 ..........................................................90 rs_rx_ctl_berclr0 ................................................................93 rs_rx_ctl_berclr1 ................................................................93 rs_rx_ctl_berclr2 ................................................................93 rs_rx_ctl_berclr3 ................................................................93 rs_rx_ctl_berclr4 ................................................................93 rs_rx_ctl_berclr5 ................................................................93 rs_rx_ctl_berclr6 ................................................................93 rs_rx_ctl_berdt0 ...................................................................93 rs_rx_ctl_berdt1 ...................................................................93 rs_rx_ctl_berdt2 ...................................................................93
200 200 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface list of objects (continued) object page object page rs_rx_ctl_berdt3 .................................................................. 93 rs_rx_ctl_berdt4 .................................................................. 93 rs_rx_ctl_berdt5 .................................................................. 93 rs_rx_ctl_berdt6 .................................................................. 93 rs_rx_ctl_berdt7 .................................................................. 93 rs_rx_ctl_berset0 ................................................................ 93 rs_rx_ctl_berset1 ................................................................ 93 rs_rx_ctl_berset2 ................................................................ 93 rs_rx_ctl_berset3 ................................................................ 93 rs_rx_ctl_berset4 ................................................................ 93 rs_rx_ctl_berset5 ................................................................ 93 rs_rx_ctl_berset6 ................................................................ 93 rs_rx_ctl_top_s0 ................................................. 88, 89, 90, 93 rs_rx_dec .................................................................................. 89 rs_rx_dscr ............................................................................... 88 rs_rx_dscr_7_16_pol ............................................................ 88 rs_rx_err0_1to0_bitcnt ...................................................... 90 rs_rx_err0_bitcnt ................................................................. 90 rs_rx_err00_0to1_bitcnt .................................................... 90 rs_rx_err01_0to1_bitcnt .................................................... 90 rs_rx_err1_1to0_bitcnt ...................................................... 90 rs_rx_err1_bitcnt ................................................................. 90 rs_rx_unc0_blkcnt ............................................................... 90 rs_rx_unc1_blkcnt ............................................................... 90 rs_rxber_clr0 ......................................................................... 93 rs_rxber_clr1 ......................................................................... 93 rs_rxber_clr2 ......................................................................... 93 rs_rxber_clr3 ......................................................................... 93 rs_rxber_clr4 ......................................................................... 93 rs_rxber_clr5 ......................................................................... 93 rs_rxber_clr6 ......................................................................... 93 rs_rxber_dettime0 ................................................................ 93 rs_rxber_dettime1 ................................................................ 93 rs_rxber_dettime2 ................................................................ 93 rs_rxber_dettime3 ................................................................ 93 rs_rxber_dettime4 ................................................................ 93 rs_rxber_dettime5 ................................................................ 93 rs_rxber_dettime6 ................................................................ 93 rs_rxber_dettime7 ................................................................ 93 rs_rxber_report ................................................................... 93 rs_rxber_sd_det ........................................................ 44, 66, 93 rs_rxber_sd_det_a ............................................................... 93 rs_rxber_sd_det_m ............................................................... 93 rs_rxber_sd_det_p ............................................................... 93 rs_rxber_sd_threshold ..................................................... 93 rs_rxber_set0 ......................................................................... 93 rs_rxber_set1 ......................................................................... 93 rs_rxber_set2 ......................................................................... 93 rs_rxber_set3 ......................................................................... 93 rs_rxber_set4 ......................................................................... 93 rs_rxber_set5 ......................................................................... 93 rs_rxber_set6 ......................................................................... 93 rs_rxber_sf_det ........................................................ 44, 66, 93 rs_rxber_sf_det_a ................................................................ 93 rs_rxber_sf_det_m ............................................................... 93 rs_rxber_sf_det_p ................................................................ 93 rs_rxber_sf_threshold ..................................................... 93 rs_state_s0 ........................................................................ 84, 93 rs_tx_ctl_errcol_s0 ............................................................ 84 rs_tx_ctl_errmsk0_s0 ......................................................... 84 rs_tx_ctl_errmsk1_s0 ......................................................... 84 rs_tx_ctl_errrept_s0 ......................................................... 84 rs_tx_ctl_errskip_s0 .......................................................... 84 rs_tx_ctl_top_s0 ....................................................... 82, 83, 84 rs_tx_enc .................................................................................. 82 rs_tx_scr .................................................................................. 83 rs_tx_scr_7_16_pol .............................................................. 83 rs_txerr .................................................................................... 84 rs_txerr_a ............................................................................... 84 rs_txerr_col .......................................................................... 84 rs_txerr_m ............................................................................... 84 rs_txerr_repeat ................................................................... 84 rs_txerr_skip ......................................................................... 84 rs_txerr_start ...................................................................... 84 rs_txerr0_mask ...................................................................... 84 rs_txerr1_mask ...................................................................... 84 rst_n ......................................................................................... 170 rsys2tsys_lb ......................................................................... 185 rtoac_clko_4 ........................................................................ 161 rtoac_datao_4 ...................................................................... 161 rtoac_synco_4 ...................................................................... 161 rw_n .................................................................................. 169, 170 rx_a1a2_inh ..................................................................... 140, 141 rx_ais_l .................................................................................... 134 rx_ais_l_a ........................................................................ 134, 139 rx_ais_l_m ............................................................................... 134 rx_ais_l_p ................................................................................ 134 rx_aisd_mode ......................................................................... 134 rx_b1bip_mode ....................................................................... 132 rx_b1calc_mode ................................................................... 166 rx_b1corrupt_enb .............................................................. 166 rx_b1corrupt_frm_cnt ..................................................... 166 rx_b1mon_mode .................................................................... 132 rx_b2corrupt_enb .............................................................. 164 rx_b2corrupt_frm_cnt ..................................................... 164 rx_cvs ...................................................................................... 132 rx_descr_mode ..................................................................... 132 rx_dw_alm ................................................................................ 36 rx_enh_frmg_enb ................................................................ 130 rx_enh_frmg_ins .......................................................... 140, 141 rx_f1_byte .............................................................................. 144 rx_f1_ndet .............................................................................. 144 rx_f1_new_a ........................................................................... 144 rx_f1_new_m .......................................................................... 144 rx_frm_mode ......................................................................... 130 rx_hw_insert_ais .......... 140, 141, 142, 143, 144, 145, 146, 147, 148 rx_inconsistent_aps .......................................................... 146 rx_inconsistent_aps_a ...................................................... 146 rx_inconsistent_aps_m ..................................................... 146 rx_inconsistent_aps_p ...................................................... 146 rx_j0_exp_0 ............................................................................. 142 rx_j0_exp_31 ........................................................................... 142 rx_j0_mismatch ..................................................................... 142 rx_j0_mismatch_a ......................................................... 139, 142 rx_j0_mismatch_m ................................................................ 142 rx_j0_mismatch_p ................................................................. 142 rx_j0_mode ..................................................................... 141, 142 rx_j0_new_a ........................................................................... 142 rx_j0_new_m ........................................................................... 142 rx_j0_sus_0 ............................................................................. 142 rx_j0_sus_31 ........................................................................... 142 rx_j0_type ....................................................................... 141, 142 rx_k_val_limit_sel ............................................................... 146 rx_k1_byte .............................................................................. 146
agere systems inc. 201 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface list of objects (continued) object page object page rx_k1_new_a ........................................................................... 146 rx_k1_new_m .......................................................................... 146 rx_k1k2ch_mismatch ........................................................... 146 rx_k1k2ch_mismatch_a ....................................................... 146 rx_k1k2ch_mismatch_m ...................................................... 146 rx_k1k2ch_mismatch_p ....................................................... 146 rx_k2_byte .............................................................................. 146 rx_k2_new_a ........................................................................... 146 rx_k2_new_m .......................................................................... 146 rx_line_ais_dis .............................................................. 116, 139 rx_line_ais_ins .............. 116, 139, 140, 144, 145, 146, 147, 148 rx_line_ais_pm ....................................................................... 134 rx_line_rdi .............................................................................. 146 rx_line_rdi_a .......................................................................... 146 rx_line_rdi_m ......................................................................... 146 rx_line_rdi_p .......................................................................... 146 rx_line_rdi_pm ....................................................................... 146 rx_loc_a .................................................................................. 139 rx_lof ................................................................................. 36, 130 rx_lof_a ........................................................................... 130, 139 rx_lof_ais_dis ....................................................... 116, 130, 139 rx_lof_m .................................................................................. 130 rx_lof_p ................................................................................... 130 rx_lof_pm ................................................................................ 130 rx_los ................................................................................. 36, 130 rx_los_a ........................................................................... 130, 139 rx_los_m .................................................................................. 130 rx_los_mode .......................................................................... 130 rx_los_p ................................................................................... 130 rx_los_pm ................................................................................ 130 rx_los_threshold ............................................................... 130 rx_ohp_mode .......................................................................... 139 rx_post_b2mon_mode ......................................................... 135 rx_post_cvl_l ....................................................................... 135 rx_post_cvl_u ....................................................................... 135 rx_post_sd_ber_sel ........................................................... 137 rx_post_sf_a ......................................................................... 139 rx_post_sf_ber_sel ............................................................ 138 rx_prbs_ber_cnt .................................................................. 163 rx_prbs_enb ........................................................................... 163 rx_prbs_inv ............................................................................ 163 rx_prbs_mode ........................................................................ 163 rx_prbs_oos .......................................................................... 163 rx_prbs_oos_a ...................................................................... 163 rx_prbs_oos_m ..................................................................... 163 rx_prbs_oos_p ...................................................................... 163 rx_prbs_type ......................................................................... 163 rx_pre_b2mon_mode ........................................................... 135 rx_pre_cvl_l .......................................................................... 135 rx_pre_cvl_u ......................................................................... 135 rx_pre_sd ................................................................................ 138 rx_pre_sd_a ........................................................................... 138 rx_pre_sd_ber_sel ...................................................... 137, 138 rx_pre_sd_m ........................................................................... 138 rx_pre_sd_p ........................................................................... 138 rx_pre_sd_sf_bipsel ........................................................... 138 rx_pre_sf ................................................................................ 138 rx_pre_sf_a ............................................................................ 138 rx_pre_sf_ber_sel .............................................................. 138 rx_pre_sf_m ........................................................................... 138 rx_pre_sf_p ............................................................................ 138 rx_reil_l ...................................................................................148 rx_reil_u ..................................................................................148 rx_rst_mon_s0 .........................................................................32 rx_rst_mon_s1 .........................................................................32 rx_rst_mon_s2 .........................................................................32 rx_rst_mon_s3 .........................................................................32 rx_s1_byte ...............................................................................147 rx_s1_ndet ...............................................................................147 rx_s1_new_a ............................................................................147 rx_s1_new_m ...........................................................................147 rx_scr_mode ..........................................................................165 rx_sdh_mode ..........................................................................139 rx_sdsf_clr_limit_4 .............................................................138 rx_sdsf_dt_unit_3 ................................................................138 rx_sdsf_dt_val_3 ..................................................................138 rx_sdsf_set_limit_3 .............................................................138 rx_sef ..................................................................................36, 130 rx_sef_a ...........................................................................130, 139 rx_sef_ais_dis ........................................................116, 130, 139 rx_sef_m ...................................................................................130 rx_sef_p ...................................................................................130 rx_sef_pm ................................................................................130 rx_sf_ais_dis ..................................................................116, 139 rx_son_alm ................................................................................36 rx_tdmx_dis .............................................................................133 rx_tim_l_ais_dis .............................................................116, 139 rx_tmx_dis ...............................................................................165 rx_toac_mode ........................................................................162 rxl_ais_byte ..................................................................47, 49, 50 rxl_ber_sd .........................................................44, 45, 46, 47, 51 rxl_ber_sf .........................................................44, 45, 46, 47, 51 rxl_bip .............................................................................46, 48, 50 rxl_fix_byte ..................................................................47, 49, 50 rxl_iae .........................................................................................51 rxl_loc ................................................................44, 45, 46, 47, 51 rxl_lof ................................................................44, 45, 46, 47, 51 rxl_los ................................................................44, 45, 46, 47, 51 rxl_oci_byte ..................................................................47, 49, 50 rxl_oof ...............................................................44, 45, 46, 47, 51 rxl_pm(tcmi)_oci/lck/ais ........................................................44 rxl_pm_stat_ais .........................................45, 46, 47, 49, 50, 51 rxl_pm_stat_lck ....................................................47, 49, 50, 51 rxl_pm_stat_oci ....................................................47, 49, 50, 51 rxl_sm_iae ..................................................................................44 rxl_tcmi_stat_ais ......................................45, 46, 47, 49, 50, 51 rxl_tcmi_stat_lck .................................................47, 49, 50, 51 rxl_tcmi_stat_oci .................................................47, 49, 50, 51 rxs_es_ovrflw ...................................................................44, 51 rxs_es_undrflw ................................................................44, 51 s sonfec_rst_mon .....................................................................32 sonfec_rx_byp_dmux ............................................................30 sonfec_rx_bypass_s0 .........130, 132, 134, 135, 164, 165, 166 sonfec_rx_dmux .....................................................................30 sonfec_rx_mode ...................130, 132, 134, 135, 139, 165, 166 sonfec_rx_tp_bypass .................................................133, 165 sonfec_rxbypdata .................................................................30 sonfec_rxdatai .......................................................................30
202 202 agere systems inc. operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface list of objects (continued) object page object page sonfec_rxdatao ..................................................................... 30 sonfec_tx_bypass_s0 ................................................. 135, 150 sonfec_tx_dmux ..................................................................... 30 sonfec_tx_mode ........................................................... 135, 150 sonfec_tx78clk ....................................................................... 30 sonfec_txdatai ....................................................................... 30 sonfec_txdatao ..................................................................... 30 sys_rx_dmux ............................................................................. 30 sys_rx_dwfec_clkmux ......................................................... 30 sys_rx_hs_clkmux ................................................................. 30 sys_rx_hsclk ........................................................................... 30 sys_rx_ls_clkmux .................................................................. 30 sys_rx_lsclk ............................................................................ 30 sys_rx_sonfec_clkmux ....................................................... 30 sys_rx78clk .............................................................................. 30 sys_rxdatao ............................................................................. 30 sys_tx_dwfec_clkmux ......................................................... 30 sys_tx_sonfec_clkmux ........................................................ 30 sys_txdatai ............................................................................... 30 t t2rf_lb ...................................................................................... 185 ta_n ............................................................................ 169, 170, 171 tclkli ........................................................................................... 34 tclksi ........................................................................................... 34 tdw2rdw_lb ............................................................................ 185 tea_n ............................................................................ 20, 169, 171 tline2rline_lb ........................................................................ 185 trsen2rrsde_lb .................................................................... 185 ts_n .................................................................................... 169, 170 tx_20frm_rdi_dis ........................................................... 117, 158 tx_a1a2_inh ...................................................................... 151, 152 tx_a2_err_ins ......................................................................... 152 tx_ais_l_a ................................................................................. 149 tx_b2mon_mode ..................................................................... 135 tx_cvl_l .................................................................................... 135 tx_cvl_u ................................................................................... 135 tx_dw_alm ................................................................................. 36 tx_enh_frmg_ins ........................................................... 151, 152 tx_f1_byte ............................................................................... 154 tx_f1_ins ................................................................................... 154 tx_hw_insert_ais ................... 150, 151, 154, 155, 156, 157, 158, 159 tx_hw_insert_rdi ........................................................................... 157 tx_inv_ptr_ins ................................................................ 156, 157 tx_j0_exp_0 .............................................................................. 153 tx_j0_exp_31 ............................................................................ 153 tx_j0_ins ................................................................................... 153 tx_k1_byte ............................................................................... 158 tx_k1k2_bypass ...................................................................... 158 tx_k2_byte ....................................................................... 117, 158 tx_line_ais_dis ............................................................... 115, 149 tx_line_ais_ins ............... 115, 150, 151, 155, 156, 157, 158, 159 tx_line_rdi ............................................................................... 134 tx_line_rdi_a .......................................................................... 134 tx_line_rdi_m .......................................................................... 134 tx_line_rdi_p .......................................................................... 134 tx_line_rdi_pm ....................................................................... 134 tx_line_uneq_ins .......................................................... 156, 157 tx_loc_a ................................................................................... 149 tx_lof .......................................................................................... 36 tx_lof_a ................................................................................... 149 tx_lof_ais_dis ............................................................... 115, 149 tx_los ......................................................................................... 36 tx_los_a ................................................................................... 149 tx_m1_ins ................................................................................. 159 tx_m1corrupt_en ................................................................. 159 tx_m1corrupt_enb .............................................................. 159 tx_m1corrupt_frm_cnt .................................................... 159 tx_ndf_ins ....................................................................... 156, 157 tx_ohp_mode .................................................................. 150, 153 tx_prbs_enb ................................................................... 156, 164 tx_prbs_inv ............................................................................ 164 tx_prbs_mode ........................................................................ 164 tx_prbs_type ................................................................. 163, 164 tx_rdi_l_sel ................................................................... 157, 158 tx_rdi_l_select .................................................................... 117 tx_rst_mon_s0 ........................................................................ 32 tx_rst_mon_s1 ........................................................................ 32 tx_rst_mon_s2 ........................................................................ 32 tx_rst_mon_s3 ........................................................................ 32 tx_s1_byte .............................................................................. 158 tx_s1_ins .................................................................................. 158 tx_sdh_mode .......................................................................... 150 tx_sef ......................................................................................... 36 tx_sef_a ................................................................................... 149 tx_sef_ais_dis ............................................................... 115, 149 tx_son_alm ............................................................................... 36 tx_toac_enb .. 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 162 tx_toac_mode ........................................................................ 162 txl_loc ........................................................................... 44, 47, 51 txl_lof ............................................................................ 44, 47, 51 txl_los ............................................................................ 44, 47, 51 txl_oof ........................................................................... 44, 47, 51 txloc ........................................................................................... 45 txs_cf .......................................................................................... 45 txs_es_ovrflw .................................................................. 44, 51 txs_es_undrflw ................................................................ 44, 51 v v10g_mode_n .......................................................................... 131 var_clk ...................................................................................... 34 var_phs ...................................................................................... 34
agere systems inc. 203 operational description july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 47 ordering information device code package temperature comcode (ordering number) TFEC0410G-3PBGA2 792-pin pbgam1th ?40 c to 85 c 700012029
copyright ? 2002 agere systems inc. all rights reserved july 2002 ds02-232sont agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. agere, agere systems, and the agere logo are trademarks of agere systems inc. for additional information, contact your agere systems account manager or the following: internet: http://www.agere.com e-mail: docmaster@agere.com n. america: agere systems inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: agere systems hong kong ltd., suites 3201 & 3210-12, 32/f, tower 2, the gateway, harbour city, kowloon tel. (852) 3129-2000 , fax (852) 3129-2020 china: (86) 21-5047-1212 (shanghai), (86) 755-2588112 (shenzhen) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 6778-8833 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 7000 624624 , fax (44) 1344 488 045 intel is a registered trademark of intel corporation. motorola is a registered trademark of motorola, inc.
hardware design guide july 2002 tfec0410g 2.5/10 gbits/s optical networking interface with strong/weak fec and digital wrapper 1 document organization this document is primarily intended for designers and engineers whom require i/o characteristics for board design of the tfec0410g optical networking interface. this is a companion document to the tfec0410g doc- ument group, which consists of the following: tfec0410g product description tfec0410g operational description tfec0410g hardware register map tfec0410g hardware design guide tfec0410g system design guide this document contains the following information, and where it can be found in this document, on the tfec0410g device: pin information (section 2 on page 3): ? pin maps (section 2.1 on page 3) ? pin descriptions (section 2.2 on page 18) absolute maximum ratings (section 3 on page 45) typical operating conditions (section 4 on page 45) thermal characteristics (section 5 on page 45) handling precautions (section 6 on page 46) electrical characteristics (section 7 on page 46) power (section 8 on page 50) timing characteristics (section 9 on page 51) test (section 10 on page 60) microprocessor interface (section 11 on page 61): ? microprocessor interface modes (section 11.2 on page 61) ? microprocessor interface timing (section 11.3 on page 62) outline diagram (section 12 on page 70) list of acronyms (section 13 on page 71) ordering information (section 14 on page 75)
table of contents contents page 2 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 1 document organization ......................................................................................................... ............................... 1 2 pin information............................................................................................................... ....................................... 3 2.1 pin maps .................................................................................................................... ..................................... 3 2.2 pin descriptions ............................................................................................................ ................................ 18 3 absolute maximum ratings ...................................................................................................... .......................... 45 4 typical operating conditions.................................................................................................. ............................ 45 5 thermal characteristics....................................................................................................... ............................... 45 6 handling precautions.......................................................................................................... ................................ 46 7 electrical characteristics .................................................................................................... ................................ 46 7.1 low-voltage differential signal (lvds) buffers.............................................................................. .............. 47 7.1.1 lvds receiver buffer capabilities......................................................................................... ................. 48 8 power......................................................................................................................... ......................................... 50 8.1 power sequencing ............................................................................................................ ............................ 50 8.2 power consumption........................................................................................................... ........................... 50 9 timing characteristics ........................................................................................................ ................................ 51 9.1 receive/transmit input data/sync interface.................................................................................. ............... 51 9.1.1 receive (line)/transmit (system) quad 2.5 gbits/s mode/10 gbits/s mode data and sync inputs ...... 51 9.1.2 transmit (line)/receive (system) quad 2.5 gbits/s/10 gbits/s data outputs........................................ 52 9.1.3 receive transport overhead access channel (rtoac) ....................................................................... 52 9.1.3.1 full toac drop mode (rx) ................................................................................................ ............... 52 9.1.3.2 partial (first sts-1) toac drop mode (rx) ............................................................................... ...... 53 9.1.4 transmit transport overhead access channel ................................................................................ ...... 55 9.1.4.1 full toac drop mode (tx) ................................................................................................ ................ 55 9.1.4.2 partial (first sts-1) toac drop mode (tx) ............................................................................... ....... 56 9.1.5 receive fec/digital wrapper receive overhead drop interface ........................................................... 57 9.1.6 transmit fec/digital wrapper insert overhead channel ...................................................................... .58 10 test......................................................................................................................... .......................................... 60 10.1 scan ....................................................................................................................... ..................................... 60 10.2 boundary scan.............................................................................................................. .............................. 60 10.3 ram bist ................................................................................................................... ................................ 60 11 microprocessor interface ..................................................................................................... ............................. 61 11.1 microprocessor interface overview.......................................................................................... ................... 61 11.2 microprocessor interface modes............................................................................................. .................... 61 11.3 microprocessor interface timing............................................................................................ ..................... 62 11.3.1 mode 1 (mpc860) .......................................................................................................... ....................... 62 11.3.2 mode 2 (mc68360)......................................................................................................... ....................... 64 11.3.3 mode 3 ( i960 (80960sx)) .................................................................................................................... .. 66 11.3.4 mode 4 (80c196, 8xc251).................................................................................................. .................. 68 11.4 use of a synchronous microprocessor with the tfec0410g in asynchronous mode ............................... 69 12 outline diagram.............................................................................................................. .................................. 70 12.1 792-pin pbgam1th ........................................................................................................... ........................ 70 13 list of acronyms ............................................................................................................. .................................. 71 14 ordering information......................................................................................................... ................................ 75
agere systems inc. 3 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information 2.1 pin maps the following tables list the pins of the tfec0410g for both 2.5 gbits/s mode and 10 gbits/s mode (see table 1 and table 2 on page 11). the 2.5 gbits/s mode pins are the first listed, in the full-size font. the second name, if present, is the pin name in 10 gbits/s mode. this 10 gbits/s pin name is in a smaller font, when appropriate. table 1. pin assignments for 792-pin pbgam1th by pin order notes: no connect refers to no connect pins. do not connect pins so designated. the second pin name (smaller font) is the pin in 10 gbits/s mode. pin name pin name pin name pin name a1 vdd b1 vdd c1 no connect d1 no connect a2 vdd b2 vdd c2 no connect d2 no connect a3 no connect b3 no connect c3 vss d3 vss a4 no connect b4 no connect c4 vss d4 vss a5 rphase_dw_3 b5 rphase_up_3 c5 no connect d5 no connect a6 ttoac_deni_1 b6 no connect c6 rphase_dw_1 d6 rphase_up_1 a7 ttoac_datai_1_2 b7 ttoac_datai_1_3 c7 rphase_dw_4 d7 rphase_up_4 a8 ttoac_deni_2 b8 no connect c8 vss d8 vdd a9 ttoac_clko_3 b9 no connect c9 ttoac_synco_2 d9 ttoac_clko_2 a10 ttoac_deni_3 b10 ttoac_synco_3 c10 ttoac_datai_2_0 d10 ttoac_datai_2_1 a11 no connect b11 no connect c11 vdd d11 vss a12 ttoac_clko_4 b12 no connect c12 ttoac_datai_3_2 d12 ttoac_datai_3_3 a13 ttoac_datai_4_0 b13 ttoac_datai_4_1 c13 ttoac_deni_4 d13 ttoac_synco_4 a14 no connect b14 no connect c14 vss d14 vdd a15 address_14 b15 address_15 c15 mpparen d15 mpdb_8_16 a16 address_10 b16 address_11 c16 address_12 d16 address_13 a17 address_6 b17 address_7 c17 vdd d17 vss a18 address_0 b18 address_1 c18 address_2 d18 address_3 a19 vss b19 vss c19 ts_n d19 ds_n a20 vdd b20 vdd c20 vdd d20 vdd a21 vss b21 vss c21 cs_n d21 rw_n a22 pclk b22 inth_n c22 mpmode_as d22 ta_n a23 data_0 b23 data_1 c23 vdd d23 vss a24 data_4 b24 data_5 c24 data_6 d24 data_7 a25 data_8 b25 data_9 c25 data_12 d25 data_13 a26 data_14 b26 data_15 c26 vss d26 vdd a27 tdw_clko_1 b27 tdw_synco_1 c27 tdw_deni_1 d27 tdw_datai_1 a28 no connect b28 no connect c28 tdw_synco_2 d28 tdw_deni_2 a29 tdw_datai_2 b29 no connect c29 vdd d29 vss a30 tdw_clko_3 b30 tdw_synco_3 c30 tdw_deni_4 d30 tdw_datai_4 a31 tdw_clko_4 b31 tdw_synco_4 c31 gpio_15 d31 gpio_14 a32 gpio_17 b32 gpio_16 c32 vss d32 vdd a33 gpio_11 b33 gpio_10 c33 gpio_7 d33 gpio_6 a34 no connect b34 no connect c34 no connect d34 no connect a35 gpio_5 b35 gpio_4 c35 no connect d35 no connect a36 no connect b36 no connect c36 vss d36 vss a37 no connect b37 no connect c37 vss d37 vss a38 vdd b38 vdd c38 no connect d38 no connect a39 vdd b39 vdd c39 no connect d39 no connect
4 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.1 pin maps (continued) table 1. pin assignments for 792-pin pbgam1th by pin order (continued) notes: no connect refers to no connect pins. do not connect pins so designated. the second pin name (smaller font) is the pin in 10 gbits/s mode. pin name pin name pin name pin name e1 no connect e21 vdd15 f1 tphase_up_2 f21 vdd15 e2 no connect e22 tea_n f2 tphase_dw_2 f22 intl_n e3 no connect e23 data_2 f3 no connect f23 data_3 e4 no connect e24 data_10 f4 no connect f24 data_11 e5 vdd15 e25 parity_1 f5 vdd15 f25 parity_0 e6 vdd15 e26 no connect f6 vdd15 f26 no connect e7 no connect e27 tdw_clko_2 f7 no connect f27 no connect e8 rphase_dw_2 e28 tdw_deni_3 f8 rphase_up_2 f28 tdw_datai_3 e9 ttoac_synco_1 e29 testmode f9 ttoac_clko_1 f29 no connect e10 ttoac_datai_1_0 e30 gpio_13 f10 ttoac_datai_1_1 f30 gpio_12 e11 ttoac_datai_2_2 e31 gpio_9 f11 ttoac_datai_2_3 f31 gpio_8 e12 no connect e32 no connect f12 no connect f32 no connect e13 ttoac_datai_3_0 e33 no connect f13 ttoac_datai_3_1 f33 no connect e14 ttoac_datai_4_2 e34 vdd15 f14 ttoac_datai_4_3 f34 vdd15 e15 mptype_im e35 vdd15 f15 pm_clk f35 vdd15 e16 no connect e36 no connect f16 no connect f36 no connect e17 address_8 e37 no connect f17 address_9 f37 no connect e18 address_4 e38 no connect f18 address_5 f38 tdlo_4_2n/ tdlo_14n e19 vdd15 e39 no connect f19 vdd15 f39 tdlo_4_2p/ tdlo_14p e20 vdd15 ? ? f20 vdd15 ? ?
agere systems inc. 5 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.1 pin maps (continued) table 1. pin assignments for 792-pin pbgam1th by pin order (continued) notes: no connect refers to no connect pins. do not connect pins so designated. the second pin name (smaller font) is the pin in 10 gbits/s mode. pin name pin name pin name pin name g1 tphase_up_1 j1 tdsi_4_1n/ tdsi_13n l1 tclksi_4n n1 tclksi_3n g2 tphase_dw_1 j2 tdsi_4_1p/ tdsi_13p l2 tclksi_4p n2 tclksi_3p g3 tphase_up_4 j3 gpio_3 l3 vss n3 tdsi_3_1n/ tdsi_9n g4 tphase_dw_4 j4 gpio_2 l4 vdd n4 tdsi_3_1p/ tdsi_9p g5 no connect j5 tphase_up_3 l5 tdsi_4_3n/ tdsi_15n n5 tdsi_3_3n/ tdsi_11n g6 no connect j6 tphase_dw_3 l6 tdsi_4_3p/ tdsi_15p n6 tdsi_3_3p/ tdsi_11p g34 no connect j34 no connect l34 vss n34 tdlo_3_1p/ tdlo_9p g35 no connect j35 no connect l35 vdd n35 tdlo_3_1n/ tdlo_9n g36 no connect j36 tdlo_3_3n/ tdlo_11n l36 vss n36 tclklo_2n g37 no connect j37 tdlo_3_3p/ tdlo_11p l37 vdd n37 tclklo_2p g38 tdlo_4_1n/ tdlo_13n j38 tdlo_2_3n/ tdlo_7n l38 tdlo_2_1n/ tdlo_5n n38 tdlo_1_2n/ tdlo_2n g39 tdlo_4_1p/ tdlo_13p j39 tdlo_2_3p/ tdlo_7p l39 tdlo_2_1p/ tdlo_5p n39 tdlo_1_2p/ tdlo_2p h1 no connect k1 tdsi_4_0n/ tdsi_12n m1 tdsi_3_2n/ tdsi_10n p1 tdsi_2_3n/ tdsi_7n h2 no connect k2 tdsi_4_0p/ tdsi_12p m2 tdsi_3_2p/ tdsi_10p p2 tdsi_2_3p/ tdsi_7p h3 vss k3 tdsi_4_2n/ tdsi_14n m3 ctap_tdsi_3 p3 vss h4 vdd k4 tdsi_4_2p/ tdsi_14p m4 ctap_tclksi_4 p4 vdd h5 no connect k5 no connect m5 no connect p5 tdsi_3_0n/ tdsi_8n h6 no connect k6 gpio_1 m6 ctap_tdsi_4 p6 tdsi_3_0p/ tdsi_8p h34 no connect k34 tdlo_4_3n/ tdlo_15n m34 tdlo_4_0p/ tdlo_12p p34 tdlo_3_0p/ tdlo_8p h35 no connect k35 tdlo_4_3p/ tdlo_15p m35 tdlo_4_0n/ tdlo_12n p35 tdlo_3_0n/ tdlo_8n h36 vdd k36 tdlo_3_2n/ tdlo_10n m36 tdlo_2_2n/ tdlo_6n p36 vdd h37 vss k37 tdlo_3_2p/ tdlo_10p m37 tdlo_2_2p/ tdlo_6p p37 vss h38 tclklo_4n k38 tclklo_3n m38 tdlo_1_3n/ tdlo_3n p38 tdlo_1_0n/ tdlo_0n h39 tclklo_4p k39 tclklo_3p m39 tdlo_1_3p/ tdlo_3p p39 tdlo_1_0p/ tdlo_0p
6 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.1 pin maps (continued) table 1. pin assignments for 792-pin pbgam1th by pin order (continued) notes: no connect refers to no connect pins. do not connect pins so designated. the second pin name (smaller font) is the pin in 10 gbits/s mode. pinnamepinnamepinnamepin name r1 tdsi_2_1n/ tdsi_5n u1 tdsi_1_3n/ tdsi_3n w1 vss aa1 vss r2 tdsi_2_1p/ tdsi_5p u2 tdsi_1_3p/ tdsi_3p w2 vss aa2 vss r3 no connect u3 vss w3 no connect aa3 tclksi_1p r4 ctap_tdsi_2 u4 vdd w34 vdd15 aa4 tclksi_1n r5 no connect u5 tclksi_2n w35 vdd15 aa5 vdd15 r6 ctap_tclksi_3 u6 tclksi_2p w36 tclkli_3n aa6 vdd15 r34 tdlo_2_0p/ tdlo_4p u34 tclkli_2n w37 tclkli_3p aa34 vdd15 r35 tdlo_2_0n/ tdlo_4n u35 tclkli_2p w38 vss aa35 vdd15 r36 tclklo_1n u36 tfrmli_1n w39 vss aa36 ctap_tclkli_4 r37 tclklo_1p u37 tfrmli_1p w4 ctap_tdsi_1 aa37 no connect r38 ctap_tclkli_1 u38 tfrmli_2n w5 vdd15 aa38 vss r39 ctap_tfrmli_1 u39 tfrmli_2p w6 vdd15 aa39 vss t1 no connect v1 tdsi_1_0n/ tdsi_0n y1 vdd ab1 ctap_tclksi_1 t2 ctap_tclksi_2 v2 tdsi_1_0p/ tdsi_0p y2 vdd ab2 ctap_rclksi_1 t3 tdsi_2_0n/ tdsi_4n v3 tdsi_1_1n/ tdsi_1n y3 vdd ab3 rclksi_1p t4 tdsi_2_0p/ tdsi_4p v4 tdsi_1_1p/ tdsi_1p y4 vdd ab4 rclksi_1n t5 tdsi_2_2n/ tdsi_6n v5 tdsi_1_2n/ tdsi_2n y5 vdd15 ab5 ctap_rclksi_2 t6 tdsi_2_2p/ tdsi_6p v6 tdsi_1_2p/ tdsi_2p y6 vdd15 ab6 no connect t34 tdlo_1_1n/ tdlo_1n v34 ctap_tfrmli_2 y34 vdd15 ab34 no connect t35 tdlo_1_1p/ tdlo_1p v35 no connect y35 vdd15 ab35 ctap_tfrmli_4 t36 tclkli_1n v36 tfrmli_3n y36 vdd ab36 tfrmli_4p t37 tclkli_1p v37 tfrmli_3p y37 vdd ab37 tfrmli_4n t38 no connect v38 ctap_tfrmli_3 y38 vdd ab38 tclkli_4p t39 ctap_tclkli_2 v39 ctap_tclkli_3 y39 vdd ab39 tclkli_4n
agere systems inc. 7 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.1 pin maps (continued) table 1. pin assignments for 792-pin pbgam1th by pin order (continued) notes: no connect refers to no connect pins. do not connect pins so designated. the second pin name (smaller font) is the pin in 10 gbits/s mode. pin name pin name pin name pin name ac1 rclksi_2p ae1 ctap_rclksi_4 ag1 rclkso_4p aj1 rdso_3_1p/ rdso_9p ac2 rclksi_2n ae2 rdso_4_2p/ rdso_14p ag2 rclkso_4n aj2 rdso_3_1n/ rdso_9n ac3 rclksi_3p ae3 rdso_4_2n/ rdso_14n ag3 rdso_3_3p/ rdso_11p aj3 vdd ac4 rclksi_3n ae4 rdso_4_0p/ rdso_12p ag4 rdso_3_3n/ rdso_11n aj4 vss ac5 vdd ae5 rdso_4_0n/ rdso_12n ag5 lvds_sreshi aj5 no connect ac6 vss ae6 no connect ag6 lvds_sreslo aj6 no connect ac34 rdli_4_2p/ rdli_14p ae34 rdli_3_2p/ rdli_10p ag34 ctap_rdli_2 aj34 rdli_1_3p/ rdli_3p ac35 rdli_4_2n/ rdli_14n ae35 rdli_3_2n/ rdli_10n ag35 no connect aj35 rdli_1_3n/ rdli_3n ac36 vss ae36 ctap_rdli_3 ag36 ctap_rclkli_3 aj36 vss ac37 vdd ae37 ctap_rclkli_4 ag37 no connect aj37 vdd ac38 rdli_4_3p/ rdli_15p ae38 ctap_rdli_4 ag38 rdli_3_1p/ rdli_9p aj38 rdli_2_2p/ rdli_6p ac39 rdli_4_3n/ rdli_15n ae39 no connect ag39 rdli_3_1n/ rdli_9n aj39 rdli_2_2n/ rdli_6n ad1 ctap_rclksi_3 af1 rdso_4_1p/ rdso_13p ah1 rdso_3_2p/ rdso_10p ak1 rdso_3_0p/ rdso_8p ad2 rclksi_4p af2 rdso_4_1n/ rdso_13n ah2 rdso_3_2n/ rdso_10n ak2 rdso_3_0n/ rdso_8n ad3 rclksi_4n af3 vss ah3 rclkso_3p ak3 rdso_2_2p/ rdso_6p ad4 rdso_4_3p/ rdso_15p af4 vdd ah4 rclkso_3n ak4 rdso_2_2n/ rdso_6n ad5 rdso_4_3n/ rdso_15n af5 lvds_sref10 ah5 rdso_2_1p/ rdso_5p ak5 rdso_1_3p/ rdso_3p ad6 no connect af6 lvds_sref14 ah6 rdso_2_1n/ rdso_5n ak6 rdso_1_3n/ rdso_3n ad34 rclkli_4p af34 rdli_3_0p/ rdli_8p ah34 rdli_2_0p/ rdli_4p ak34 rdli_1_0p/ rdli_0p ad35 rclkli_4n af35 rdli_3_0n/ rdli_8n ah35 rdli_2_0n/ rdli_4n ak35 rdli_1_0n/ rdli_0n ad36 rdli_4_0p/ rdli_12p af36 vdd ah36 rdli_2_3p/ rdli_7p ak36 no connect ad37 rdli_4_0n/ rdli_12n af37 vss ah37 rdli_2_3n/ rdli_7n ak37 ctap_rclkli_2 ad38 rdli_4_1p/ rdli_13p af38 rdli_3_3p/ rdli_11p ah38 rclkli_3p ak38 rdli_2_1p/ rdli_5p ad39 rdli_4_1n/ rdli_13n af39 rdli_3_3n/ rdli_11n ah39 rclkli_3n ak39 rdli_2_1n/ rdli_5n
8 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.1 pin maps (continued) table 1. pin assignments for 792-pin pbgam1th by pin order (continued) notes: no connect refers to no connect pins. do not connect pins so designated. the second pin name (smaller font) is the pin in 10 gbits/s mode. pin name pin name pin name pin name al1 rdso_2_3p/ rdso_7p am34 no connect ap1 rdso_1_1p/ rdso_1p ap20 vdd15 al2 rdso_2_3n/ rdso_7n am35 no connect ap2 rdso_1_1n/ rdso_1n ap21 vdd15 al3 rclkso_2p am36 vdd ap3 no connect ap22 no connect al4 rclkso_2n am37 vss ap4 no connect ap23 no connect al5 rdso_1_0p/ rdso_0p am38 rdli_1_2p/ rdli_2p ap5 vdd15 ap24 no connect al6 rdso_1_0n/ rdso_0n am39 rdli_1_2n/ rdli_2n ap6 vdd15 ap25 rdw_synco_1 al34 no connect an1 rdso_1_2p/ rdso_2p ap7 no connect ap26 no connect al35 ctap_rclkli_1 an2 rdso_1_2n/ rdso_2n ap8 gpio_18 ap27 no connect al36 rdli_1_1p/ rdli_1p an3 rclkso_1p ap9 gpio_22 ap28 no connect al37 rdli_1_1n/ rdli_1n an4 rclkso_1n ap10 tdi ap29 no connect al38 rclkli_2p an5 no connect ap11 rtoac_dato_1_2 ap30 no connect al39 rclkli_2n an6 no connect ap12 rtoac_dato_2_2 ap31 lvds_lref14 am1 rdso_2_0p/ rdso_4p an34 no connect ap13 rtoac_dato_3_2 ap32 lvds_lreslo am2 rdso_2_0n/ rdso_4n an35 no connect ap14 rtoac_dato_4_2 ap33 rxrefo_2n am3 vss an36 rxrefo_1p ap15 gpio_25 ap34 vdd15 am4 vdd an37 rxrefo_1n ap16 gpio_31 ap35 vdd15 am5 no connect an38 no connect ap17 gpio_37 ap36 no connect am6 no connect an39 ctap_rdli_1 ap18 gpio_41 ap37 no connect ? ? ? ? ap19 vdd15 ap38 rclkli_1p ? ? ? ? ? ? ap39 rclkli_1n
agere systems inc. 9 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.1 pin maps (continued) table 1. pin assignments for 792-pin pbgam1th by pin order (continued) notes: no connect refers to no connect pins. do not connect pins so designated. the second pin name (smaller font) is the pin in 10 gbits/s mode. pinnamepinnamepinnamepinname ar1 no connect at1 no connect au1 no connect av1 vdd ar2 no connect at2 no connect au2 no connect av2 vdd ar3 no connect at3 vss au3 vss av3 no connect ar4 no connect at4 vss au4 vss av4 no connect ar5 vdd15 at5 no connect au5 no connect av5 gpio_20 ar6 vdd15 at6 no connect au6 no connect av6 gpio_24 ar7 no connect at7 no connect au7 no connect av7 tms ar8 gpio_19 at8 vdd au8 vss av8 rtoac_dato_1_0 ar9 gpio_23 at9 rtoac_synco_1 au9 rtoac_clko_1 av9 rtoac_dato_2_0 ar10 tck at10 rtoac_synco_2 au10 rtoac_clko_2 av10 rtoac_synco_3 ar11 rtoac_dato_1_3 at11 vss au11 vdd av11 no connect ar12 rtoac_dato_2_3 at12 rtoac_dato_3_0 au12 rtoac_dato_3_1 av12 rtoac_synco_4 ar13 rtoac_dato_3_3 at13 rtoac_dato_4_0 au13 rtoac_dato_4_1 av13 no connect ar14 rtoac_dato_4_3 at14 vdd au14 vss av14 gpio_27 ar15 gpio_26 at15 gpio_29 au15 gpio_30 av15 gpio_33 ar16 gpio_32 at16 no connect au16 no connect av16 gpio_35 ar17 gpio_38 at17 vss au17 vdd av17 gpio_39 ar18 gpio_42 at18 gpio_43 au18 gpio_44 av18 no connect ar19 vdd15 at19 gpio_45 au19 gpio_46 av19 vss ar20 vdd15 at20 vdd au20 vdd av20 vdd ar21 vdd15 at21 no connect au21 no connect av21 vss ar22 no connect at22 rst_n au22 iddq_n av22 gpio_48 ar23 no connect at23 vss au23 vdd av23 no connect ar24 no connect at24 no connect au24 no connect av24 no connect ar25 rdw_clko_1 at25 no connect au25 no connect av25 no connect ar26 rdw_datao_1 at26 vdd au26 vss av26 no connect ar27 no connect at27 no connect au27 rdw_clko_2 av27 no connect ar28 no connect at28 no connect au28 rdw_clko_3 av28 rdw_datao_2 ar29 no connect at29 vss au29 vdd av29 no connect ar30 no connect at30 no connect au30 no connect av30 rdw_clko_4 ar31 lvds_lref10 at31 no connect au31 no connect av31 rdw_datao_4 ar32 lvds_lreshi at32 vdd au32 vss av32 no connect ar33 rxrefo_2p at33 no connect au33 no connect av33 no connect ar34 vdd15 at34 rxrefo_4n au34 rxrefo_4p av34 scanclk1 ar35 vdd15 at35 no connect au35 no connect av35 no connect ar36 no connect at36 vss au36 vss av36 rxrefo_3n ar37 no connect at37 vss au37 vss av37 no connect ar38 no connect at38 no connect au38 no connect av38 vdd ar39 no connect at39 no connect au39 no connect av39 vdd
10 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.1 pin maps (continued) table 1. pin assignments for 792-pin pbgam1th by pin order (continued) notes: no connect refers to no connect pins. do not connect pins so designated. the second pin name (smaller font) is the pin in 10 gbits/s mode. pin name pin name pin name pin name aw1 vdd aw11 no connect aw21 vss aw31 rdw_synco_4 aw2 vdd aw12 rtoac_clko_4 aw22 gpio_47 aw32 no connect aw3 no connect aw13 no connect aw23 no connect aw33 no connect aw4 no connect aw14 gpio_28 aw24 no connect aw34 scanclk2 aw5 gpio_21 aw15 gpio_34 aw25 no connect aw35 no connect aw6 tdo aw16 gpio_36 aw26 no connect aw36 rxrefo_3p aw7 trst_n aw17 gpio_40 aw27 no connect aw37 no connect aw8 rtoac_dato_1_1 aw18 no connect aw28 rdw_synco_2 aw38 vdd aw9 rtoac_dato_2_1 aw19 vss aw29 rdw_synco_3 aw39 vdd aw10 rtoac_clko_3 aw20 vdd aw30 rdw_datao_3 ? ?
agere systems inc. 11 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.1 pin maps (continued) table 2. pin assignments for 792-pin pbgam1th by signal name order notes: no connect refers to no connect pins. do not connect pins so designated. the second pin name (smaller font) is the pin in 10 gbits/s mode. pin name pin name pin name pin name a18 address_0 r39 ctap_tfrmli_1 aw5 gpio_21 c15 mpparen b18 address_1 v34 ctap_tfrmli_2 ap9 gpio_22 e15 mptype_im c18 address_2 v38 ctap_tfrmli_3 ar9 gpio_23 b11 no connect d18 address_3 ab35 ctap_tfrmli_4 av6 gpio_24 b12 no connect e18 address_4 a23 data_0 ap15 gpio_25 b14 no connect f18 address_5 b23 data_1 ar15 gpio_26 b28 no connect a17 address_6 e23 data_2 av14 gpio_27 b29 no connect b17 address_7 f23 data_3 aw14 gpio_28 b3 no connect e17 address_8 a24 data_4 at15 gpio_29 b34 no connect f17 address_9 b24 data_5 au15 gpio_30 b36 no connect a16 address_10 c24 data_6 ap16 gpio_31 b37 no connect b16 address_11 d24 data_7 ar16 gpio_32 b4 no connect c16 address_12 a25 data_8 av15 gpio_33 b6 no connect d16 address_13 b25 data_9 aw15 gpio_34 b8 no connect a15 address_14 e24 data_10 av16 gpio_35 b9 no connect b15 address_15 f24 data_11 aw16 gpio_36 a11 no connect c21 cs_n c25 data_12 ap17 gpio_37 a14 no connect al35 ctap_rclkli_1 d25 data_13 ar17 gpio_38 a28 no connect ak37 ctap_rclkli_2 a26 data_14 av17 gpio_39 a3 no connect ag36 ctap_rclkli_3 b26 data_15 aw17 gpio_40 a34 no connect ae37 ctap_rclkli_4 d19 ds_n ap18 gpio_41 a36 no connect ab2 ctap_rclksi_1 k6 gpio_1 ar18 gpio_42 a37 no connect ab5 ctap_rclksi_2 j4 gpio_2 at18 gpio_43 a4 no connect ad1 ctap_rclksi_3 j3 gpio_3 au18 gpio_44 aa37 no connect ae1 ctap_rclksi_4 b35 gpio_4 at19 gpio_45 ab34 no connect an39 ctap_rdli_1 a35 gpio_5 au19 gpio_46 ab6 no connect ag34 ctap_rdli_2 d33 gpio_6 aw22 gpio_47 ad6 no connect ae36 ctap_rdli_3 c33 gpio_7 av22 gpio_48 ae39 no connect ae38 ctap_rdli_4 f31 gpio_8 au22 iddq_n ae6 no connect r38 ctap_tclkli_1 e31 gpio_9 b22 inth_n ag35 no connect t39 ctap_tclkli_2 b33 gpio_10 f22 intl_n ag37 no connect v39 ctap_tclkli_3 a33 gpio_11 ar31 lvds_lref10 aj5 no connect aa36 ctap_tclkli_4 f30 gpio_12 ap31 lvds_lref14 aj6 no connect ab1 ctap_tclksi_1 e30 gpio_13 ar32 lvds_lreshi ak36 no connect t2 ctap_tclksi_2 d31 gpio_14 ap32 lvds_lreslo al34 no connect r6 ctap_tclksi_3 c31 gpio_15 af5 lvds_sref10 am34 no connect m4 ctap_tclksi_4 b32 gpio_16 af6 lvds_sref14 am35 no connect w4 ctap_tdsi_1 a32 gpio_17 ag5 lvds_sreshi am5 no connect r4 ctap_tdsi_2 ap8 gpio_18 ag6 lvds_sreslo am6 no connect m3 ctap_tdsi_3 ar8 gpio_19 d15 mpdb_8_16 an34 no connect m6 ctap_tdsi_4 av5 gpio_20 c22 mpmode_as an35 no connect
12 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.1 pin maps (continued) table 2. pin assignments for 792-pin pbgam1th by signal name order (continued) notes: no connect refers to no connect pins. do not connect pins so designated. the second pin name (smaller font) is the pin in 10 gbits/s mode. pin name pin name pin name pin name an38 no connect at28 no connect av4 no connect e38 no connect an5 no connect at30 no connect aw11 no connect e39 no connect an6 no connect at31 no connect aw13 no connect e4 no connect ap22 no connect at33 no connect aw18 no connect e7 no connect ap23 no connect at35 no connect aw23 no connect f12 no connect ap24 no connect at38 no connect aw24 no connect f16 no connect ap26 no connect at39 no connect aw25 no connect f26 no connect ap27 no connect at5 no connect aw26 no connect f27 no connect ap28 no connect at6 no connect aw27 no connect f29 no connect ap29 no connect at7 no connect aw3 no connect f3 no connect ap3 no connect au1 no connect aw32 no connect f32 no connect ap30 no connect au16 no connect aw33 no connect f33 no connect ap36 no connect au2 no connect aw35 no connect f36 no connect ap37 no connect au21 no connect aw37 no connect f37 no connect ap4 no connect au24 no connect aw4 no connect f4 no connect ap7 no connect au25 no connect c1 no connect f7 no connect ar1 no connect au30 no connect c2 no connect g34 no connect ar2 no connect au31 no connect c34 no connect g35 no connect ar22 no connect au33 no connect c35 no connect g36 no connect ar23 no connect au35 no connect c38 no connect g37 no connect ar24 no connect au38 no connect c39 no connect g5 no connect ar27 no connect au39 no connect c5 no connect g6 no connect ar28 no connect au5 no connect d1 no connect h1 no connect ar29 no connect au6 no connect d2 no connect h2 no connect ar3 no connect au7 no connect d34 no connect h34 no connect ar30 no connect av11 no connect d35 no connect h35 no connect ar36 no connect av13 no connect d38 no connect h5 no connect ar37 no connect av18 no connect d39 no connect h6 no connect ar38 no connect av23 no connect d5 no connect j34 no connect ar39 no connect av24 no connect e1 no connect j35 no connect ar4 no connect av25 no connect e12 no connect k5 no connect ar7 no connect av26 no connect e16 no connect m5 no connect at1 no connect av27 no connect e2 no connect r3 no connect at16 no connect av29 no connect e26 no connect r5 no connect at2 no connect av3 no connect e3 no connect t1 no connect at21 no connect av32 no connect e32 no connect t38 no connect at24 no connect av33 no connect e33 no connect v35 no connect at25 no connect av35 no connect e36 no connect w3 no connect at27 no connect av37 no connect e37 no connect ? ?
agere systems inc. 13 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.1 pin maps (continued) table 2. pin assignments for 792-pin pbgam1th by signal name order (continued) notes: no connect refers to no connect pins. do not connect pins so designated. the second pin name (smaller font) is the pin in 10 gbits/s mode. pin name pin name pin name pin name f25 parity_0 an4 rclkso_1n ah34 rdli_2_0p/ rdli_4p al6 rdso_1_0n/ rdso_0n e25 parity_1 an3 rclkso_1p ak38 rdli_2_1p/ rdli_5p ap2 rdso_1_1n/ rdso_1n a22 pclk al4 rclkso_2n aj38 rdli_2_2p/ rdli_6p an2 rdso_1_2n/ rdso_2n f15 pm_clk al3 rclkso_2p ah36 rdli_2_3p/ rdli_7p ak6 rdso_1_3n/ rdso_3n ap39 rclkli_1n ah4 rclkso_3n af35 rdli_3_0n/ rdli_8n al5 rdso_1_0p/ rdso_0p ap38 rclkli_1p ah3 rclkso_3p ag39 rdli_3_1n/ rdli_9n ap1 rdso_1_1p/ rdso_1p al39 rclkli_2n ag2 rclkso_4n ae35 rdli_3_2n/ rdli_10n an1 rdso_1_2p/ rdso_2p al38 rclkli_2p ag1 rclkso_4p af39 rdli_3_3n/ rdli_11n ak5 rdso_1_3p/ rdso_3p ah39 rclkli_3n ak35 rdli_1_0n/ rdli_0n af34 rdli_3_0p/ rdli_8p am2 rdso_2_0n/ rdso_4n ah38 rclkli_3p al37 rdli_1_1n/ rdli_1n ag38 rdli_3_1p/ rdli_9p ah6 rdso_2_1n/ rdso_5n ad35 rclkli_4n am39 rdli_1_2n/ rdli_2n ae34 rdli_3_2p/ rdli_10p ak4 rdso_2_2n/ rdso_6n ad34 rclkli_4p aj35 rdli_1_3n/ rdli_3n af38 rdli_3_3p/ rdli_11p al2 rdso_2_3n/ rdso_7n ab4 rclksi_1n ak34 rdli_1_0p/ rdli_0p ad37 rdli_4_0n/ rdli_12n am1 rdso_2_0p/ rdso_4p ab3 rclksi_1p al36 rdli_1_1p/ rdli_1p ad39 rdli_4_1n/ rdli_13n ah5 rdso_2_1p/ rdso_5p ac2 rclksi_2n am38 rdli_1_2p/ rdli_2p ac35 rdli_4_2n/ rdli_14n ak3 rdso_2_2p/ rdso_6p ac1 rclksi_2p aj34 rdli_1_3p/ rdli_3p ac39 rdli_4_3n/ rdli_15n al1 rdso_2_3p/ rdso_7p ac4 rclksi_3n ah35 rdli_2_0n/ rdli_4n ad36 rdli_4_0p/ rdli_12p ak2 rdso_3_0n/ rdso_8n ac3 rclksi_3p ak39 rdli_2_1n/ rdli_5n ad38 rdli_4_1p/ rdli_13p aj2 rdso_3_1n/ rdso_9n ad3 rclksi_4n aj39 rdli_2_2n/ rdli_6n ac34 rdli_4_2p/ rdli_14p ah2 rdso_3_2n/ rdso_10n ad2 rclksi_4p ah37 rdli_2_3n/ rdli_7n ac38 rdli_4_3p/ rdli_15p ag4 rdso_3_3n/ rdso_11n
14 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.1 pin maps (continued) table 2. pin assignments for 792-pin pbgam1th by signal name order (continued) notes: no connect refers to no connect pins. do not connect pins so designated. the second pin name (smaller font) is the pin in 10 gbits/s mode. pin name pin name pin name pin name ak1 rdso_3_0p/ rdso_8p aw29 rdw_synco_3 ar12 rtoac_datao_2_3 av34 scanclk1 aj1 rdso_3_1p/ rdso_9p aw31 rdw_synco_4 at12 rtoac_datao_3_0 aw34 scanclk2 ah1 rdso_3_2p/ rdso_10p c6 rphase_dw_1 au12 rtoac_datao_3_1 d22 ta_n ag3 rdso_3_3p/ rdso_11p e8 rphase_dw_2 ap13 rtoac_datao_3_2 ar10 tck ae5 rdso_4_0n/ rdso_12n a5 rphase_dw_3 ar13 rtoac_datao_3_3 t36 tclkli_1n af2 rdso_4_1n/ rdso_13n c7 rphase_dw_4 at13 rtoac_datao_4_0 t37 tclkli_1p ae3 rdso_4_2n/ rdso_14n d6 rphase_up_1 au13 rtoac_datao_4_1 u34 tclkli_2n ad5 rdso_4_3n/ rdso_15n f8 rphase_up_2 ap14 rtoac_datao_4_2 u35 tclkli_2p ae4 rdso_4_0p/ rdso_12p b5 rphase_up_3 ar14 rtoac_datao_4_3 w36 tclkli_3n af1 rdso_4_1p/ rdso_13p d7 rphase_up_4 at9 rtoac_synco_1 w37 tclkli_3p ae2 rdso_4_2p/ rdso_14p at22 rst_n at10 rtoac_synco_2 ab39 tclkli_4n ad4 rdso_4_3p/ rdso_15p au9 rtoac_clko_1 av10 rtoac_synco_3 ab38 tclkli_4p ar25 rdw_clko_1 au10 rtoac_clko_2 av12 rtoac_synco_4 r36 tclklo_1n au27 rdw_clko_2 aw10 rtoac_clko_3 d21 rw_n r37 tclklo_1p au28 rdw_clko_3 aw12 rtoac_clko_4 an37 rxrefo_1n n36 tclklo_2n av30 rdw_clko_4 av8 rtoac_datao_1_0 an36 rxrefo_1p n37 tclklo_2p ar26 rdw_datao_1 aw8 rtoac_datao_1_1 ap33 rxrefo_2n k38 tclklo_3n av28 rdw_datao_2 ap11 rtoac_datao_1_2 ar33 rxrefo_2p k39 tclklo_3p aw30 rdw_datao_3 ar11 rtoac_datao_1_3 av36 rxrefo_3n h38 tclklo_4n av31 rdw_datao_4 av9 rtoac_datao_2_0 aw36 rxrefo_3p h39 tclklo_4p ap25 rdw_synco_1 aw9 rtoac_datao_2_1 at34 rxrefo_4n aa4 tclksi_1n aw28 rdw_synco_2 ap12 rtoac_datao_2_2 au34 rxrefo_4p aa3 tclksi_1p
agere systems inc. 15 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.1 pin maps (continued) table 2. pin assignments for 792-pin pbgam1th by signal name order (continued) notes: no connect refers to no connect pins. do not connect pins so designated. the second pin name (smaller font) is the pin in 10 gbits/s mode. pin name pin name pin name pin name u5 tclksi_2n l39 tdlo_2_1p/ tdlo_5p v1 tdsi_1_0n/ tdsi_0n p6 tdsi_3_0p/ tdsi_8p u6 tclksi_2p m37 tdlo_2_2p/ tdlo_6p v3 tdsi_1_1n/ tdsi_1n n4 tdsi_3_1p/ tdsi_9p n1 tclksi_3n j39 tdlo_2_3p/ tdlo_7p v5 tdsi_1_2n/ tdsi_2n m2 tdsi_3_2p/ tdsi_10p n2 tclksi_3p p35 tdlo_3_0n/ tdlo_8n u1 tdsi_1_3n/ tdsi_3n n6 tdsi_3_3p/ tdsi_11p l1 tclksi_4n n35 tdlo_3_1n/ tdlo_9n v2 tdsi_1_0p/ tdsi_0p k1 tdsi_4_0n/ tdsi_12n l2 tclksi_4p k36 tdlo_3_2n/ tdlo_10n v4 tdsi_1_1p/ tdsi_1p j1 tdsi_4_1n/ tdsi_13n ap10 tdi j36 tdlo_3_3n/ tdlo_11n v6 tdsi_1_2p/ tdsi_2p k3 tdsi_4_2n/ tdsi_14n p38 tdlo_1_0n/ tdlo_0n p34 tdlo_3_0p/ tdlo_8p u2 tdsi_1_3p/ tdsi_3p l5 tdsi_4_3n/ tdsi_15n t34 tdlo_1_1n/ tdlo_1n n34 tdlo_3_1p/ tdlo_9p t3 tdsi_2_0n/ tdsi_4n k2 tdsi_4_0p/ tdsi_12p n38 tdlo_1_2n/ tdlo_2n k37 tdlo_3_2p/ tdlo_10p r1 tdsi_2_1n/ tdsi_5n j2 tdsi_4_1p/ tdsi_13p m38 tdlo_1_3n/ tdlo_3n j37 tdlo_3_3p/ tdlo_11p t5 tdsi_2_2n/ tdsi_6n k4 tdsi_4_2p/ tdsi_14p p39 tdlo_1_0p/ tdlo_0p m35 tdlo_4_0n/ tdlo_12n p1 tdsi_2_3n/ tdsi_7n l6 tdsi_4_3p/ tdsi_15p t35 tdlo_1_1p/ tdlo_1p g38 tdlo_4_1n/ tdlo_13n t4 tdsi_2_0p/ tdsi_4p a27 tdw_clko_1 n39 tdlo_1_2p/ tdlo_2p f38 tdlo_4_2n/ tdlo_14n r2 tdsi_2_1p/ tdsi_5p e27 tdw_clko_2 m39 tdlo_1_3p/ tdlo_3p k34 tdlo_4_3n/ tdlo_15n t6 tdsi_2_2p/ tdsi_6p a30 tdw_clko_3 r35 tdlo_2_0n/ tdlo_4n m34 tdlo_4_0p/ tdlo_12p p2 tdsi_2_3p/ tdsi_7p a31 tdw_clko_4 l38 tdlo_2_1n/ tdlo_5n g39 tdlo_4_1p/ tdlo_13p p5 tdsi_3_0n/ tdsi_8n d27 tdw_datai_1 m36 tdlo_2_2n/ tdlo_6n f39 tdlo_4_2p/ tdlo_14p n3 tdsi_3_1n/ tdsi_9n a29 tdw_datai_2 j38 tdlo_2_3n/ tdlo_7n k35 tdlo_4_3p/ tdlo_15p m1 tdsi_3_2n/ tdsi_10n f28 tdw_datai_3 r34 tdlo_2_0p/ tdlo_4p aw6 tdo n5 tdsi_3_3n/ tdsi_11n d30 tdw_datai_4
16 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.1 pin maps (continued) table 2. pin assignments for 792-pin pbgam1th by signal name order (continued) notes: no connect refers to no connect pins. do not connect pins so designated. the second pin name (smaller font) is the pin in 10 gbits/s mode. pin name pin name pin name pin name c27 tdw_deni_1 e10 ttoac_datai_1_0 b39 vdd am36 vdd d28 tdw_deni_2 f10 ttoac_datai_1_1 c11 vdd am4 vdd e28 tdw_deni_3 a7 ttoac_datai_1_2 c17 vdd at14 vdd c30 tdw_deni_4 b7 ttoac_datai_1_3 c20 vdd at20 vdd b27 tdw_synco_1 c10 ttoac_datai_2_0 c23 vdd at26 vdd c28 tdw_synco_2 d10 ttoac_datai_2_1 c29 vdd at32 vdd b30 tdw_synco_3 e11 ttoac_datai_2_2 d14 vdd at8 vdd b31 tdw_synco_4 f11 ttoac_datai_2_3 d20 vdd au11 vdd e22 tea_n e13 ttoac_datai_3_0 d26 vdd au17 vdd e29 testmode f13 ttoac_datai_3_1 d32 vdd au20 vdd u36 tfrmli_1n c12 ttoac_datai_3_2 d8 vdd au23 vdd u37 tfrmli_1p d12 ttoac_datai_3_3 h36 vdd au29 vdd u38 tfrmli_2n a13 ttoac_datai_4_0 h4 vdd av1 vdd u39 tfrmli_2p b13 ttoac_datai_4_1 l35 vdd av2 vdd v36 tfrmli_3n e14 ttoac_datai_4_2 l37 vdd av20 vdd v37 tfrmli_3p f14 ttoac_datai_4_3 l4 vdd av38 vdd ab37 tfrmli_4n a6 ttoac_deni_1 p36 vdd av39 vdd ab36 tfrmli_4p a8 ttoac_deni_2 p4 vdd aw1 vdd av7 tms a10 ttoac_deni_3 u4 vdd aw2 vdd g2 tphase_dw_1 c13 ttoac_deni_4 y1 vdd aw20 vdd f2 tphase_dw_2 e9 ttoac_synco_1 y2 vdd aw38 vdd j6 tphase_dw_3 c9 ttoac_synco_2 y3 vdd aw39 vdd g4 tphase_dw_4 b10 ttoac_synco_3 y4 vdd aa5 vdd15 g1 tphase_up_1 d13 ttoac_synco_4 y36 vdd aa6 vdd15 f1 tphase_up_2 a1 vdd y37 vdd aa34 vdd15 j5 tphase_up_3 a2 vdd y38 vdd aa35 vdd15 g3 tphase_up_4 a20 vdd y39 vdd ap19 vdd15 aw7 trst_n a38 vdd ac37 vdd ap20 vdd15 c19 ts_n a39 vdd ac5 vdd ap21 vdd15 f9 ttoac_clko_1 b1 vdd af36 vdd ap34 vdd15 d9 ttoac_clko_2 b2 vdd af4 vdd ap35 vdd15 a9 ttoac_clko_3 b20 vdd aj3 vdd ap5 vdd15 a12 ttoac_clko_4 b38 vdd aj37 vdd ap6 vdd15
agere systems inc. 17 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.1 pin maps (continued) table 2. pin assignments for 792-pin pbgam1th by signal name order (continued) notes: no connect refers to no connect pins. do not connect pins so designated. the second pin name (smaller font) is the pin in 10 gbits/s mode. pin name pin name pin name pin name ar19 vdd15 w5 vdd15 at17 vss c36 vss ar20 vdd15 w6 vdd15 at23 vss c37 vss ar21 vdd15 y34 vdd15 at29 vss c4 vss ar34 vdd15 y35 vdd15 at3 vss c8 vss ar35 vdd15 y5 vdd15 at36 vss d11 vss ar5 vdd15 y6 vdd15 at37 vss d17 vss ar6 vdd15 b19 vss at4 vss d23 vss e19 vdd15 b21 vss au14 vss d29 vss e20 vdd15 a19 vss au26 vss d3 vss e21 vdd15 a21 vss au3 vss d36 vss e34 vdd15 aa1 vss au32 vss d37 vss e35 vdd15 aa2 vss au36 vss d4 vss e5 vdd15 aa38 vss au37 vss h3 vss e6 vdd15 aa39 vss au4 vss h37 vss f19 vdd15 ac36 vss au8 vss l3 vss f20 vdd15 ac6 vss av19 vss l34 vss f21 vdd15 af3 vss av21 vss l36 vss f34 vdd15 af37 vss aw19 vss p3 vss f35 vdd15 aj36 vss aw21 vss p37 vss f5 vdd15 aj4 vss c14 vss u3 vss f6 vdd15 am3 vss c26 vss w1 vss w34 vdd15 am37 vss c3 vss w2 vss w35 vdd15 at11 vss c32 vss w38 vss ??????w39vss
18 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions the following tables outline the individual pin descriptions grouped by functionality. table 3. pin descriptions?system control pin symbol type * * o = output, i u = input with internal pull-up resistor. i/o are 5 v compatible, 3.3 v ttl. they will tolerate 5 v at their inputs or outputs. the value of all internal pull-up resistors is 100 k ? . ? input with 50 k ? pull-up resistor. name/description au22 iddq_n i u global pin 3-state control (active-low). this input incorporates hysteresis. 0 = all outputs assume a high-impedance state (except for jtag test data output (tdo)). 1 = normal operation. at22 rst_n i u asynchronous chip reset (active-low). this input incorporates hysteresis. to ensure proper reset, this input should be held low for a minimum of 26 ns. the device will not come out of reset until a clock is provided. 0 = causes an asynchronous reset of the device. 1 = normal operation. c22 mpmode_as i ? microprocessor mode. 1 = synchronous mode. 0 = asynchronous mode. e15 mptype_im i ? microprocessor intel ? / motorola ? mode. 1 = motorola interface. 0 = intel interface. d15 mpdb_8_16 i ? microprocessor data bus size. 1 = 16-bit data bus. 0 = 8-bit data bus. c15 mpparen i ? microprocessor parity ignore control. 1 = check parity during read/write operations. 0 = ignore parity failures during read/write operations. f15 pm_clk i u /o one second performance monitoring clock. the performance monitoring registers are updated on the rising edge of this signal. the internal pm anomaly counters are cleared at the same time. pm_clk must be high for at least 250 ns, and low for at least 250 ns. the period of the performance monitoring clock will normally be 1 s, but the minimum period required for proper operation is 500 ns (during testing and development, for example).
agere systems inc. 19 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 4. pin descriptions?transmit phase detectors table 5. pin descriptions?receive phase detectors pin symbol type * * o = output. i/o are 5 v compatible, 3.3 v ttl. they will tolerate 5 v at their inputs or outputs. name/description g2 tphase_dw_1 o transmit phase detector output channel 1. ? quad 2.5 gbits/s mode?used. ? 10 gbits/s mode?used. g1 tphase_up_1 o f2 tphase_dw_2 o transmit phase detector output channel 2. ? quad 2.5 gbits/s mode?used. ? 10 gbits/s mode?not used. f1 tphase_up_2 o j6 tphase_dw_3 o transmit phase detector output channel 3. ? quad 2.5 gbits/s mode?used. ? 10 gbits/s mode?not used. j5 tphase_up_3 o g4 tphase_dw_4 o transmit phase detector output channel 4. ? quad 2.5 gbits/s mode?used. ? 10 gbits/s mode?not used. g3 tphase_up_4 o pin symbol type * * o = output. i/o are 5 v compatible, 3.3 v ttl. they will tolerate 5 v at their inputs or outputs. name/description c6 rphase_dw_1 o receive phase detector output channel 1. ? quad 2.5 gbits/s mode?used. ? 10 gbits/s mode?used. d6 rphase_up_1 o e8 rphase_dw_2 o receive phase detector output channel 2. ? quad 2.5 gbits/s mode?used. ? 10 gbits/s mode?not used. f8 rphase_up_2 o a5 rphase_dw_3 o receive phase detector output channel 3. ? quad 2.5 gbits/s mode?used. ? 10 gbits/s mode?not used. b5 rphase_up_3 o c7 rphase_dw_4 o receive phase detector output channel 4. ? quad 2.5 gbits/s mode?used. ? 10 gbits/s mode?not used. d7 rphase_up_4 o
20 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 6. pin descriptions?receive line interface pin 10 g mode symbol 2.5 g mode symbol type * * i = input, o = output, lvds = low-voltage differential signal. name/description ap38 ap39 rclkli_1p rclkli_1n rclkli_1p rclkli_1n i lvds receive line interface channel 1. ? quad 2.5 gbits/s mode?clock (666/622 mhz). ? 10 gbits/s mode?clock (669/622 mhz). an36 an37 rxrefo_1p rxrefo_1n rxrefo_1p rxrefo_1n o lvds receive line interface channel 1. ? quad 2.5 gbits/s mode?line timing reference (8 khz). ? 10 gbits/s mode?line timing reference (8 khz). ak34 ak35 rdli_0p rdli_0n rdli_1_0p rdli_1_0n i lvds receive line interface channel 1. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 0 (lsb). al36 al37 rdli_1p rdli_1n rdli_1_1p rdli_1_1n i lvds receive line interface channel 1. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 1. am38 am39 rdli_2p rdli_2n rdli_1_2p rdli_1_2n i lvds receive line interface channel 1. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 2. aj34 aj35 rdli_3p rdli_3n rdli_1_3p rdli_1_3n i lvds receive line interface channel 1. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 3. al38 al39 ? rclkli_2p rclkli_2n i lvds receive line interface channel 2. ? quad 2.5 gbits/s mode?clock (666/622 mhz). ? 10 gbits/s mode?not used. ar33 ap33 ? rxrefo_2p rxrefo_2n o lvds receive line interface channel 2. ? quad 2.5 gbits/s mode?line timing reference (8 khz). ? 10 gbits/s mode?not used. ah34 ah35 rdli_4p rdli_4n rdli_2_0p rdli_2_0n i lvds receive line interface channel 2. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 4. ak38 ak39 rdli_5p rdli_5n rdli_2_1p rdli_2_1n i lvds receive line interface channel 2. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 5. aj38 aj39 rdli_6p rdli_6n rdli_2_2p rdli_2_2n i lvds receive line interface channel 2. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 6. ah36 ah37 rdli_7p rdli_7n rdli_2_3p rdli_2_3n i lvds receive line interface channel 2. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 7.
agere systems inc. 21 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 6. pin descriptions?receive line interface (continued) pin 10 g mode symbol 2.5 g mode symbol type * * i = input, o = output, lvds = low-voltage differential signal. name/description ah38 ah39 ? rclkli_3p rclkli_3n i lvds receive line interface channel 3. ? quad 2.5 gbits/s mode?clock (666/622 mhz). ? 10 gbits/s mode?not used. aw36 av36 ? rxrefo_3p rxrefo_3n o lvds receive line interface channel 3. ? quad 2.5 gbits/s mode?line timing reference (8 khz). ? 10 gbits/s mode?not used. af34 af35 rdli_8p rdli_8n rdli_3_0p rdli_3_0n i lvds receive line interface channel 3. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 8. ag38 ag39 rdli_9p rdli_9n rdli_3_1p rdli_3_1n i lvds receive line interface channel 3. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 9. ae34 ae35 rdli_10p rdli_10n rdli_3_2p rdli_3_2n i lvds receive line interface channel 3. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 10. af38 af39 rdli_11p rdli_11n rdli_3_3p rdli_3_3n i lvds receive line interface channel 3. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 11. ad34 ad35 ? rclkli_4p rclkli_4n i lvds receive line interface channel 4. ? quad 2.5 gbits/s mode?clock (666/622 mhz). ? 10 gbits/s mode?not used. au34 at34 ? rxrefo_4p rxrefo_4n o lvds receive line interface channel 4. ? quad 2.5 gbits/s mode?line timing reference (8 khz). ? 10 gbits/s mode?not used. ad36 ad37 rdli_12p rdli_12n rdli_4_0p rdli_4_0n i lvds receive line interface channel 4. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 12. ad38 ad39 rdli_13p rdli_13n rdli_4_1p rdli_4_1n i lvds receive line interface channel 4. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 13. ac34 ac35 rdli_14p rdli_14n rdli_4_2p rdli_4_2n i lvds receive line interface channel 4. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 14. ac38 ac39 rdli_15p rdli_15n rdli_4_3p rdli_4_3n i lvds receive line interface channel 4. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 15 (msb).
22 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 7. pin descriptions?lvds reference, line interface pin symbol type * * i = input. name/description an39 ctap_rdli1 i center tap for rdli_1 inputs. provides center-tapped common-mode ter- mination. this input should be terminated through an external 0.01 f capacitor to ground (see rdli_[0:3]/rdli_1_[0:3], table 6 on page 20). ag34 ctap_rdli2 i center tap for rdli_2 inputs. provides center-tapped common-mode ter- mination. this input should be terminated through an external 0.01 f capacitor to ground (see rdli_[4:7]/rdli_2_[4:7], table 6 on page 20). ae36 ctap_rdli3 i center tap for rdli_3 inputs. provides center-tapped common-mode ter- mination. this input should be terminated through an external 0.01 f capacitor to ground (see rdli_[8:11]/rdli_3_[8:11], table 6 on page 21). ae38 ctap_rdli4 i center tap for rdli_4 inputs. provides center-tapped common-mode termi- nation. this input should be terminated through an external 0.01 f capacitor to ground (see rdli_[12:15]/rdli_4_[12:15], table 6 on page 21). al35 ctap_rclkli1 i center tap for rclkli_1 input. provides center-tapped common-mode ter- mination. this input should be terminated through an external 0.01 f capacitor to ground (see rclkli_1, table 6 on page 20). ak37 ctap_rclkli2 i center tap for rclkli_2 input. provides center-tapped common-mode ter- mination. this input should be terminated through an external 0.01 f capacitor to ground (see rclkli_2, table 6 on page 20). ag36 ctap_rclkli3 i center tap for rclkli_3 input. provides center-tapped common-mode ter- mination. this input should be terminated through an external 0.01 f capacitor to ground (see rclkli_3, table 6 on page 21). ae37 ctap_rclkli4 i center tap for rclkli_4 input. provides center-tapped common-mode ter- mination. this input should be terminated through an external 0.01 f capacitor to ground (see rclkli_4, table 6 on page 21). ab2 ctap_rclksi1 i center tap for rclksi_1 input. provides center-tapped common-mode ter- mination. this input should be terminated through an external 0.01 f capacitor to ground (see rclksi_1, table 8 on page 23). ab5 ctap_rclksi2 i center tap for rclksi_2 input. provides center-tapped common-mode ter- mination. this input should be terminated through an external 0.01 f capacitor to ground (see rclksi_2, table 8 on page 23). ad1 ctap_rclksi3 i center tap for rclksi_3 input. provides center-tapped common-mode ter- mination. this input should be terminated through an external 0.01 f capacitor to ground (see rclksi_3, table 8 on page 24). ae1 ctap_rclksi4 i center tap for rclksi_4 input. provides center-tapped common-mode ter- mination. this input should be terminated through an external 0.01 f capacitor to ground (see rclksi_4, table 8 on page 24). ar31 lvds_lref10 i 1.0 v 3% reference voltage for line-side lvds interface i/os. note: a suggested schematic diagram is given in figure 1 on page 28. ap31 lvds_lref14 i 1.4 v 3% reference voltage for line-side lvds interface i/os. note: a suggested schematic diagram is given in figure 1 on page 28. ar32 lvds_lreshi i connect a 100 ? 1% resistor between these pins. ap32 lvds_lreslo i
agere systems inc. 23 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 8. pin descriptions?receive system interface pin 10 g mode symbol 2.5 g mode symbol type * * i = input, o = output, lvds = low-voltage differential signal. name/description ab3 ab4 rclksi_1p rclksi_1n rclksi_1p rclksi_1n i lvds receive system interface channel 1. ? quad 2.5 gbits/s mode?input clock (622 mhz). ? 10 gbits/s mode?input clock (622 mhz). an3 an4 rclkso_1p rclkso_1n rclkso_1p rclkso_1n o lvds receive system interface channel 1. ? quad 2.5 gbits/s mode?output clock (622 mhz). ? 10 gbits/s mode?output clock (622 mhz). al5 al6 rdso_0p rdso_0n rdso_1_0p rdso_1_0n o lvds receive system interface channel 1. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 0 (lsb). ap1 ap2 rdso_1p rdso_1n rdso_1_1p rdso_1_1n o lvds receive system interface channel 1. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 1. an1 an2 rdso_2p rdso_2n rdso_1_2p rdso_1_2n o lvds receive system interface channel 1. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 2. ak5 ak6 rdso_3p rdso_3n rdso_1_3p rdso_1_3n o lvds receive system interface channel 1. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 3. ac1 ac2 ?rclksi_2p rclksi_2n i lvds receive system interface channel 2. ? quad 2.5 gbits/s mode?input clock (622 mhz). ? 10 gbits/s mode?not used. al3 al4 ?rclkso_2p rclkso_2n o lvds receive system interface channel 2. ? quad 2.5 gbits/s mode?output clock (622 mhz). ? 10 gbits/s mode?not used. am1 am2 rdso_4p rdso_4n rdso_2_0p rdso_2_0n o lvds receive system interface channel 2. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 4. ah5 ah6 rdso_5p rdso_5n rdso_2_1p rdso_2_1n o lvds receive system interface channel 2. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 5. ak3 ak4 rdso_6p rdso_6n rdso_2_2p rdso_2_2n o lvds receive system interface channel 2. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 6. al1 al2 rdso_7p rdso_7n rdso_2_3p rdso_2_3n o lvds receive system interface channel 2. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 7.
24 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 8. pin descriptions?receive system interface (continued) pin 10 g mode symbol 2.5 g mode symbol type* * i = input, o = output, lvds = low-voltage differential signal. name/description ac3 ac4 ?rclksi_3p rclksi_3n i lvds receive system interface channel 3. ? quad 2.5 gbits/s mode?input clock (622 mhz). ? 10 gbits/s mode?not used. ah3 ah4 ?rclkso_3p rclkso_3n o lvds receive system interface channel 3. ? quad 2.5 gbits/s mode?output clock (622 mhz). ? 10 gbits/s mode?not used. ak1 ak2 rdso_8p rdso_8n rdso_3_0p rdso_3_0n o lvds receive system interface channel 3. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 8. aj1 aj2 rdso_9p rdso_9n rdso_3_1p rdso_3_1n o lvds receive system interface channel 3. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 9. ah1 ah2 rdso_10p rdso_10n rdso_3_2p rdso_3_2n o lvds receive system interface channel 3. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 10. ag3 ag4 rdso_11p rdso_11n rdso_3_3p rdso_3_3n o lvds receive system interface channel 3. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 11. ad2 ad3 ?rclksi_4p rclksi_4n i lvds receive system interface channel 4. ? quad 2.5 gbits/s mode?input clock (622 mhz). ? 10 gbits/s mode?not used. ag1 ag2 ?rclkso_4p rclkso_4n o lvds receive system interface channel 4. ? quad 2.5 gbits/s mode?output clock (622 mhz). ? 10 gbits/s mode?not used. ae4 ae5 rdso_12p rdso_12n rdso_4_0p rdso_4_0n o lvds receive system interface channel 4. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 12. af1 af2 rdso_13p rdso_13n rdso_4_1p rdso_4_1n o lvds receive system interface channel 4. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 13. ae2 ae3 rdso_14p rdso_14n rdso_4_2p rdso_4_2n o lvds receive system interface channel 4. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 14. ad4 ad5 rdso_15p rdso_15n rdso_4_3p rdso_4_3n o lvds receive system interface channel 4. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 15 (msb).
agere systems inc. 25 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 9. pin descriptions?transmit system interface pin 10 g mode symbol 2.5 g mode symbol type * * i = input, o = output, lvds = low-voltage differential signal. name/description aa3 aa4 tclksi_1p tclksi_1n tclksi_1p tclksi_1n i lvds transmit system interface channel 1. ? quad 2.5 gbits/s mode?clock (622 mhz). ? 10 gbits/s mode?clock (622 mhz). v2 v1 tdsi_0p tdsi_0n tdsi_1_0p tdsi_1_0n i lvds transmit system interface channel 1. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 0 (lsb). v4 v3 tdsi_1p tdsi_1n tdsi_1_1p tdsi_1_1n i lvds transmit system interface channel 1. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 1. v6 v5 tdsi_2p tdsi_2n tdsi_1_2p tdsi_1_2n i lvds transmit system interface channel 1. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 2. u2 u1 tdsi_3p tdsi_3n tdsi_1_3p tdsi_1_3n i lvds transmit system interface channel 1. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 3. u6 u5 ? tclksi_2p tclksi_2n i lvds transmit system interface channel 2. ? quad 2.5 gbits/s mod?clock (622 mhz). ? 10 gbits/s mode?not used. t4 t3 tdsi_4p tdsi_4n tdsi_2_0p tdsi_2_0n i lvds transmit system interface channel 2. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 4. r2 r1 tdsi_5p tdsi_5n tdsi_2_1p tdsi_2_1n i lvds transmit system interface channel 2. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 5. t6 t5 tdsi_6p tdsi_6n tdsi_2_2p tdsi_2_2n i lvds transmit system interface channel 2. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 6. p2 p1 tdsi_7p tdsi_7n tdsi_2_3p tdsi_2_3n i lvds transmit system interface channel 2. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 7.
26 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 9. pin descriptions?transmit system interface (continued) pin 10 g mode symbol 2.5 g mode symbol type * * i = input, o = output, lvds = low-voltage differential signal. name/description n2 n1 ? tclksi_3p tclksi_3n i lvds transmit system interface channel 3. ? quad 2.5 gbits/s mode?clock (622 mhz). ? 10 gbits/s mode?not used. p6 p5 tdsi_8p tdsi_8n tdsi_3_0p tdsi_3_0n i lvds transmit system interface channel 3. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 8. n4 n3 tdsi_9p tdsi_9n tdsi_3_1p tdsi_3_1n i lvds transmit system interface channel 3. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 9. m2 m1 tdsi_10p tdsi_10n tdsi_3_2p tdsi_3_2n i lvds transmit system interface channel 3. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 10. n6 n5 tdsi_11p tdsi_11n tdsi_3_3p tdsi_3_3n i lvds transmit system interface channel 3. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 11. l2 l1 ? tclksi_4p tclksi_4n i lvds transmit system interface channel 4. ? quad 2.5 gbits/s mode?clock (622 mhz). ? 10 gbits/s mode?not used. k2 k1 tdsi_12p tdsi_12n tdsi_4_0p tdsi_4_0n i lvds transmit system interface channel 4. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 12. j2 j1 tdsi_13p tdsi_13n tdsi_4_1p tdsi_4_1n i lvds transmit system interface channel 4. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 13. k4 k3 tdsi_14p tdsi_14n tdsi_4_2p tdsi_4_2n i lvds transmit system interface channel 4. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 14. l6 l5 tdsi_15p tdsi_15n tdsi_4_3p tdsi_4_3n i lvds transmit system interface channel 4. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 15 (msb).
agere systems inc. 27 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 10. pin descriptions?lvds reference, transmit system/line interface pin symbol type * name/description w4 ctap_tdsi_1 i center tap for tdsi_1 inputs. provides center-tapped common-mode ter- mination. this input should be terminated through an external 0.01 f capacitor to ground (see tdsi_[0:3]/tdsi_1_[3:0], table 9 on page 25). r4 ctap_tdsi_2 i center tap for tdsi_2 inputs. provides center-tapped common-mode ter- mination. this input should be terminated through an external 0.01 f capacitor to ground (see tdsi_[4:7]/tdsi_2_[3:0], table 9 on page 25). m3 ctap_tdsi_3 i center tap for tdsi_3 inputs. provides center-tapped common-mode ter- mination. this input should be terminated through an external 0.01 f capacitor to ground (see tdsi_[8:11]/tdsi_3_[3:0], table 9 on page 26). m6 ctap_tdsi_4 i center tap for tdsi_4 inputs. provides center-tapped common-mode ter- mination. this input should be terminated through an external 0.01 f capacitor to ground (see tdsi_[12:15]/tdsi_4_[3:0], table 9 on page 26). ab1 ctap_tclksi_1 i center tap for tclksi_1 input. provides center-tapped common-mode termination. this input should be terminated through an external 0.01 f capacitor to ground (see tclksi_1, table 9 on page 25). t2 ctap_tclksi_2 i center tap for tclksi_2 input. provides center-tapped common-mode termination. this input should be terminated through an external 0.01 f capacitor to ground (see tclksi_2, table 9 on page 25). r6 ctap_tclksi_3 i center tap for tclksi_3 input. provides center-tapped common-mode termination. this input should be terminated through an external 0.01 f capacitor to ground (see tclksi_3, table 9 on page 26). m4 ctap_tclksi_4 i center tap for tclksi_4 input. provides center-tapped common-mode termination. this input should be terminated through an external 0.01 f capacitor to ground (see tclksi_4, table 9 on page 26). r38 ctap_tclkli_1 i center tap for tclkli_1 input. provides center-tapped common-mode termination. this input should be terminated through an external 0.01 f capacitor to ground (see tclkli_1, table 11 on page 29). t39 ctap_tclkli_2 i center tap for tclkli_2 input. provides center-tapped common-mode termination. this input should be terminated through an external 0.01 f capacitor to ground (see tclkli_2, table 11 on page 29). v39 ctap_tclkli_3 i center tap for tclkli_3 input. provides center-tapped common-mode termination. this input should be terminated through an external 0.01 f capacitor to ground (see tclkli_3, table 11 on page 30). aa36 ctap_tclkli_4 i center tap for tclkli_4 input. provides center-tapped common-mode termination. this input should be terminated through an external 0.01 f capacitor to ground (see tclkli_4, table 11 on page 30). r39 ctap_tfrmli_1 i center tap for tfrmli_1 input. provides center-tapped common-mode termination. this input should be terminated through an external 0.01 f capacitor to ground (see tfrmli_1, table 11 on page 29). v34 ctap_tfrmli_2 i center tap for tfrmli_2 input. provides center-tapped common-mode termination. this input should be terminated through an external 0.01 f capacitor to ground (see tfrmli_2, table 11 on page 29). v38 ctap_tfrmli_3 i center tap for tfrmli_3 input. provides center-tapped common-mode termination. this input should be terminated through an external 0.01 f capacitor to ground (see tfrmli_3, table 11 on page 30). * i = input.
28 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface figure 1. suggested schematic for 1.0 v and 1.4 v reference voltages ab35 ctap_tfrmli_4 i center tap for tfrmli_4 input. provides center-tapped common-mode termination. this input should be terminated through an external 0.01 f capacitor to ground (see tfrmli_4, table 11 on page 30). af5 lvds_sref10 i 1.0 v 3% reference voltage for system-side lvds interface i/os. note: a suggested schematic diagram is given in figure 1. af6 lvds_sref14 i 1.4 v 3% reference voltage for system-side lvds interface i/os. note: a suggested schematic diagram is given in figure 1. ag5 lvds_sreshi i connect a 100 ? 1% resistor between these pins. ag6 lvds_sreslo i * i = input. 2 pin information (continued) 2.2 pin descriptions (continued) table 10. pin descriptions?lvds reference, transmit system/line interface (continued) pin symbol type * name/description 3.3 v 2.32 k ? 1% 1 k ? 1% 10 nf 3.3 v 1.91 k ? 1% 1.43 k ? 1% 10 nf lvdsref10 lvdsref14
agere systems inc. 29 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 11. pin descriptions?transmit line interface pin 10 gbits/s mode symbol 2.5 gbits/s mode symbol type * * i = input, o = output, lvds = low-voltage differential signal. name/description t37 t36 tclkli_1p tclkli_1n tclkli_1p tclkli_1n i lvds transmit line interface channel 1. ? quad 2.5 gbits/s mode?input clock (666/669/622 mhz). ? 10 gbits/s mode?input clock (669/622 mhz). u37 u36 tfrmli_1p tfrmli_1n tfrmli_1p tfrmli_1n i lvds transmit line interface channel 1. ? quad 2.5 gbits/s mode?dw frame alignment frame sync. ? 10 gbits/s mode?dw frame alignment frame sync (any multiple of the dw frame rate). r37 r36 tclklo_1p tclklo_1n tclklo_1p tclklo_1n o lvds transmit line interface channel 1. ? quad 2.5 gbits/s mode?output clock (666/669/622 mhz). ? 10 gbits/s mode?output clock (669/622 mhz) p39 p38 tdlo_0p tdlo_0n tdlo_1_0p tdlo_1_0n o lvds transmit line interface channel 1. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 0 (lsb). t35 t34 tdlo_1p tdlo_1n tdlo_1_1p tdlo_1_1n o lvds transmit line interface channel 1. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 1. n39 n38 tdlo_2p tdlo_2n tdlo_1_2p tdlo_1_2n o lvds transmit line interface channel 1. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 2. m39 m38 tdlo_3p tdlo_3n tdlo_1_3p tdlo_1_3n o lvds transmit line interface channel 1. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 3. u35 u34 ?tclkli_2p tclkli_2n i lvds transmit line interface channel 2. ? quad 2.5 gbits/s mode?clock (666/622 mhz). ? 10 gbits/s mode?not used. u39 u38 ? tfrmli_2p tfrmli_2n i lvds transmit line interface channel 2. ? quad 2.5 gbits/s mode?dw frame alignment frame sync. ? 10 gbits/s mode?not used. n37 n36 ?tclko_2p tclko_2n o lvds transmit line interface channel 2. ? quad 2.5 gbits/s mode?output clock (666/622 mhz). ? 10 gbits/s mode?not used. r34 r35 tdlo_4p tdlo_4n tdlo_2_0p tdlo_2_0n o lvds transmit line interface channel 2. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 4. l39 l38 tdlo_5p tdlo_5n tdlo_2_1p tdlo_2_1n o lvds transmit line interface channel 2. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 5. m37 m36 tdlo_6p tdlo_6n tdlo_2_2p tdlo_2_2n o lvds transmit line interface channel 2. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 6. j39 j38 tdlo_7p tdlo_7n tdlo_2_3p tdlo_2_3n o lvds transmit line interface channel 2. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 7.
30 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 11. pin descriptions?transmit line interface (continued) pin 10 gbits/s mode symbol 2.5 gbits/s mode symbol type * * i = input, o = output, lvds = low-voltage differential signal. name/description w37 w36 ?tclkli_3p tclkli_3n i lvds transmit line interface channel 3. ? quad 2.5 gbits/s mode?input clock (666/622 mhz). ? 10 gbits/s mode?not used. v37 v36 ?tfrmli_3p tfrmli_3n i lvds transmit line interface channel 3. ? quad 2.5 gbits/s mode?dw frame alignment frame sync. ? 10 gbits/s mode?not used. k39 k38 ?tclklo_3p tclklo_3n o lvds transmit line interface channel 3. ? quad 2.5 gbits/s mode?output clock (666/622 mhz). ? 10 gbits/s mode?not used. p34 p35 tdlo_8p tdlo_8n tdlo_3_0p tdlo_3_0n o lvds transmit line interface channel 3. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 8. n34 n35 tdlo_9p tdlo_9n tdlo_3_1p tdlo_3_1n o lvds transmit line interface channel 3. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 9. k37 k36 tdlo_10p tdlo_10n tdlo_3_2p tdlo_3_2n o lvds transmit line interface channel 3. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 10. j37 j36 tdlo_11p tdlo_11n tdlo_3_3p tdlo_3_3n o lvds transmit line interface channel 3. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 11. ab38 ab39 ?tclkli_4p tclkli_4n i lvds transmit line interface channel 4. ? quad 2.5 gbits/s mode?clock (666/622 mhz). ? 10 gbits/s mode?not used. ab36 ab37 ?tfrmli_4p tfrmli_4n i lvds transmit line interface channel 4. ? quad 2.5 gbits/s mode?dw frame alignment frame sync. ? 10 gbits/s mode?not used. h39 h38 ?tclklo_4p tclklo_4n o lvds transmit line interface channel 4. ? quad 2.5 gbits/s mode?output clock (666/622 mhz). ? 10 gbits/s mode?not used. m34 m35 tdlo_12p tdlo_12n tdlo_4_0p tdlo_4_0n o lvds transmit line interface channel 4. ? quad 2.5 gbits/s mode?bit 0 (lsb). ? 10 gbits/s mode?bit 12. g39 g38 tdlo_13p tdlo_13n tdlo_4_1p tdlo_4_1n o lvds transmit line interface channel 4. ? quad 2.5 gbits/s mode?bit 1. ? 10 gbits/s mode?bit 13. f39 f38 tdlo_14p tdlo_14n tdlo_4_2p tdlo_4_2n o lvds transmit line interface channel 4. ? quad 2.5 gbits/s mode?bit 2. ? 10 gbits/s mode?bit 14. k35 k34 tdlo_15p tdlo_15n tdlo_4_3p tdlo_4_3n o lvds transmit line interface channel 4. ? quad 2.5 gbits/s mode?bit 3 (msb). ? 10 gbits/s mode?bit 15 (msb).
agere systems inc. 31 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 12. pin descriptions?receive section/line overhead interface (drop) pin symbol type * * o = output. all i/o are 5 v compatible, 3.3 v ttl. they will tolerate 5 v at their inputs or outputs. ? the frequencies in the parenthesis are for full mode and partial mode, respectively. name/description au9 rtoac_clko_1 o receive channel 1 toac drop clock. ? quad 2.5 gbits/s mode?toac drop clock (20.736/1.728 mhz) ? . ? 10 gbits/s mode?toac drop clock (20.736 mhz/not used) ? . at9 rtoac_synco_1 o receive channel 1 toac drop sync. ? quad 2.5 gbits/s mode?toac drop sync (8/8 khz) ? . ? 10 gbits/s mode?toac drop sync (8 khz/not used) ? . av8 rtoac_datao_1_0 o receive channel 1 toac drop data. ? quad 2.5 gbits/s mode?toac drop data (20.736/1.728[0] mbits/s) ? (in partial toac mode, only bit 0 is valid). ? 10 gbits/s mode?toac drop data (20.736 mbits/s/not used) ? . note: msb = bit 3, lsb = bit 0, valid in both quad 2.5 gbits/s/10 gbits/s [sts-1s, #145?192] modes. aw8 rtoac_datao_1_1 o ap11 rtoac_datao_1_2 o ar11 rtoac_datao_1_3 o au10 rtoac_clko_2 o receive channel 2 toac drop clock. ? quad 2.5 gbits/s mode?toac drop clock (20.736/1.728 mhz) ? . ? 10 gbits/s mode?toac drop clock (20.736 mhz/not used) ? . at10 rtoac_synco_2 o receive channel 2 toac drop sync. ? quad 2.5 gbits/s mode?toac drop sync (8/8 khz) ? . ? 10 gbits/s mode?toac drop sync (8 khz/not used) ? . av9 rtoac_datao_2_0 o receive channel 2 toac drop data. ? quad 2.5 gbits/s mode?toac drop data (20.736/1.728[0] mbits/s) ? (in partial toac mode, only bit 0 is valid). ? 10 gbits/s mode?toac drop data (20.736 mbits/s/not used) ? . note: msb= bit 3, lsb = bit 0, valid in both quad 2.5 gbits/s/10 gbits/s [sts-1s, #97?144] modes. aw9 rtoac_datao_2_1 o ap12 rtoac_datao_2_2 o ar12 rtoac_datao_2_3 o
32 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 12. pin descriptions?receive section/line overhead interface (drop) (continued) pin symbol type * * o = output. all i/o are 5 v compatible, 3.3 v ttl. they will tolerate 5 v at their inputs or outputs. ? the frequencies in the parenthesis are for full mode and partial mode, respectively. name/description aw10 rtoac_clko_3 o receive channel 3 toac drop clock. ? quad 2.5 gbits/s mode?toac drop clock (20.736/1.728 mhz) ? . ? 10 gbits/s mode?toac drop clock (20.736 mhz/not used) ? . av10 rtoac_synco_3 o receive channel 3 toac drop sync. ? quad 2.5 gbits/s mode?toac drop sync (8/8 khz) ? . ? 10 gbits/s mode?toac drop sync (8 khz/not used) ? . at12 rtoac_datao_3_0 o receive channel 3 toac drop data. ? quad 2.5 gbits/s mode?toac serial drop data (20.736/1.728[0] mbits/s ? ; in partial toac mode, only bit 0 is valid). ? 10 gbits/s mode?toac serial drop data (20.736 mbits/s/not used) ? . note: msb = bit 3, lsb = bit 0, valid in both quad 2.5 gbits/s/10 gbits/s [sts-1s, #49?96] modes. au12 rtoac_datao_3_1 o ap13 rtoac_datao_3_2 o ar13 rtoac_datao_3_3 o aw12 rtoac_clko_4 o receive channel 4 toac drop clock. ? quad 2.5 gbits/s mode?toac drop clock (20.736/1.728 mhz) ? . ? 10 gbits/s mode?toac drop clock (20.736/1.728 mhz) ? . av12 rtoac_synco_4 o receive channel 4 toac drop sync. ? quad 2.5 gbits/s mode?toac drop sync (8/8 khz) ? . ? 10 gbits/s mode?toac drop sync (8/8 khz) ? . at13 rtoac_datao_4_0 o receive channel 4 toac drop data. ? quad 2.5 gbits/s mode?toac serial drop data (20.736/1.728[0] mbits/s) ? (in partial toac mode, only bit 0 is valid). ? 10 gbits/s mode?toac serial drop data (20.736/1.728 mbits/s) ? . note: msb = bit 3, lsb = bit 0, valid in both quad 2.5 gbits/s/10 gbits/s [sts-1s, #1?48] modes. au13 rtoac_datao_4_1 o ap14 rtoac_datao_4_2 o ar14 rtoac_datao_4_3 o
agere systems inc. 33 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 13. pin descriptions?transmit section/line overhead interface (insert) pin symbol type * * o = output, i d = input with internal pull-down resistor. all i/o are 5 v compatible, 3.3 v ttl. they will tolerate 5 v at their inputs or output s. the value of all internal pull-down resistors is 50 k ? . ? the frequencies in the parenthesis are for full mode and partial mode, respectively. name/description f9 ttoac_clko_1 o transmit channel 1 toac insert clock. ? quad 2.5 gbits/s mode?toac insert clock (20.736/1.728 mhz) ? . ? 10 gbits/s mode?toac insert clock (20.736 mhz/not used) ? . e9 ttoac_synco_1 o transmit channel 1 toac insert sync. ? quad 2.5 gbits/s mode?toac insert sync (8/8 khz) ? . ? 10 gbits/s mode?toac insert sync (8 khz/not used) ? . a6 ttoac_deni_1 i d transmit channel 1 toac insert enable. ? quad 2.5 gbits/s mode?toac insert enable. ? 10 gbits/s mode?toac insert enable. e10 ttoac_datai_1_0 i d transmit channel 1 toac data. ? quad 2.5 gbits/s mode?toac data (20.736/1.728 [0] mbits/s) ? . ? 10 gbits/s mode?toac data (20.736 mbits/s/not used) ? . note: msb = bit 3, lsb = bit 0, valid in both quad 2.5 gbits/s/10 gbits/s [sts-1s, #145?192] modes. f10 ttoac_datai_1_1 i d a7 ttoac_datai_1_2 i d b7 ttoac_datai_1_3 i d d9 ttoac_clko_2 o transmit channel 2 toac insert clock. ? quad 2.5 gbits/s mode?toac insert clock (20.736/1.728 mhz) ? . ? 10 gbits/s mode?toac insert clock (20.736 mhz/not used) ? . c9 ttoac_synco_2 o transmit channel 2 toac insert sync. ? quad 2.5 gbits/s mode?toac insert sync (8/8 khz) ? . ? 10 gbits/s mode?toac insert sync (8 khz/not used) ? . a8 ttoac_deni_2 i d transmit channel 2 toac insert enable. ? quad 2.5 gbits/s mode?toac insert enable. ? 10 gbits/s mode?toac insert enable. c10 ttoac_datai_2_0 i d transmit channel 2 toac data. ? quad 2.5 gbits/s mode?toac data (20.736/1.728 [0] mbits/s) ? . ? 10 gbits/s mode?toac data (20.736 mbits/s/not used) ? . note: msb = bit 3, lsb = bit 0, valid in both quad 2.5 gbits/s/10 gbits/s [sts-1s, #97?144] modes. d10 ttoac_datai_2_1 i d e11 ttoac_datai_2_2 i d f11 ttoac_datai_2_3 i d
34 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 13. pin descriptions?transmit section/line overhead interface (insert) (continued) pin symbol type * * o = output, i d = input with internal pull-down resistor. all i/o are 5 v compatible, 3.3 v ttl. they will tolerate 5 v at their inputs or output s. the value of all internal pull-down resistors is 50 k ? . ? the frequencies in the parenthesis are for full mode and partial mode, respectively. name/description a9 ttoac_clko_3 o transmit channel 3 toac insert clock. ? quad 2.5 gbits/s mode?toac insert clock (20.736/1.728 mhz) ? . ? 10 gbits/s mode?toac insert clock (20.736 mhz/not used) ? . b10 ttoac_synco_3 o transmit channel 3 toac insert sync. ? quad 2.5 gbits/s mode?toac insert sync (8/8 khz) ? . ? 10 gbits/s mode?toac insert sync (8 khz/not used) ? . a10 ttoac_deni_3 i d transmit channel 3 toac insert enable. ? quad 2.5 gbits/s mode?toac insert enable. ? 10 gbits/s mode?toac insert enable. e13 ttoac_datai_3_0 i d transmit channel 3 toac data. ? quad 2.5 gbits/s mode?toac data (20.736/1.728[0] mbits/s) ? . ? 10 gbits/s mode?toac data (20.736 mbits/s/not used) ? . note: msb = bit 3, lsb = bit 0, valid in both quad 2.5 gbits/s/10 gbits/s [sts-1s, #49?96] modes. f13 ttoac_datai_3_1 i d c12 ttoac_datai_3_2 i d d12 ttoac_datai_3_3 i d a12 ttoac_clko_4 o transmit channel 4 toac insert clock. ? quad 2.5 gbits/s mode?toac insert clock (20.736/1.728 mhz) ? . ? 10 gbits/s mode?toac insert clock (20.736/1.728 mhz) ? . d13 ttoac_synco_4 o transmit channel 4 toac insert sync. ? quad 2.5 gbits/s mode?toac insert sync (8/8 khz) ? . ? 10 gbits/s mode?toac insert sync (8/8 khz) ? . c13 ttoac_deni_4 i d transmit channel 4 toac insert enable. ? quad 2.5 gbits/s mode?toac insert enable. ? 10 gbits/s mode? toac insert enable. a13 ttoac_datai_4_0 i d transmit channel 4 toac data. ? quad 2.5 gbits/s mode?toac data (20.736/1.728[0] mbits/s) ? . ? 10 gbits/s mode?toac data (20.736/1.728 mbits/s) ? . note: msb = bit 3, lsb = bit 0, valid in both quad 2.5 gbits/s/10 gbits/s [sts-1s, #1?48] modes. b13 ttoac_datai_4_1 i d e14 ttoac_datai_4_2 i d f14 ttoac_datai_4_3 i d
agere systems inc. 35 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 14. pin descriptions?receive fec/digital wrapper overhead drop (fec/dw) interface pin symbol type * * o = output. all i/o are 5 v compatible, 3.3 v ttl. they will tolerate 5 v at their inputs or outputs. ? the frequencies in the parenthesis are the fec rate and dw rate, respectively. name/description ar25 rdw_clko_1 o receive dwac channel 1 drop clock. ? quad 2.5 gbits/s mode?fec/dw drop clock (~10.455/~10.455 mhz) ? . ? 10 gbits/s mode?fec/dw drop clock (~10.455/~10.455 mhz) ? . ap25 rdw_synco_1 o receive dwac channel 1 drop superframe sync. ? quad 2.5 gbits/s mode?fec/dw drop superframe sync (~81.68/~20.42 khz) ? . ? 10 gbits/s mode?fec/dw drop superframe sync (~326.7/~81.68 khz) ? . ar26 rdw_datao_1 o receive dwac channel 1 drop data. ? quad 2.5 gbits/s mode?fec/dw drop data (~10.455 mbits/s) ? . ? 10 gbits/s mode?fec/dw drop data bit 1 of 4 (lsb) (~10.455 mbits/s) ? . au27 rdw_clko_2 o receive dwac channel 2 drop clock. ? quad 2.5 gbits/s mode?fec/dw drop clock (~10.455 mhz) ? . ? 10 gbits/s mode?not used. aw28 rdw_synco_2 o receive dwac channel 2 drop superframe sync. ? quad 2.5 gbits/s mode?fec/dw drop superframe sync (~81.68/~20.42 khz) ? . ? 10 gbits/s mode?not used . av28 rdw_datao_2 o receive dwac channel 2 drop data. ? quad 2.5 gbits/s mode?fec/dw drop data (~10.455 mhz) ? . ? 10 gbits/s mode?fec/dw drop data bit 2 of 4 (~10.455 mbits/s) ? . au28 rdw_clko_3 o receive dwac channel 3 drop clock. ? quad 2.5 gbits/s mode?fec/dw drop clock (~10.455 mhz) ? . ? 10 gbits/s mode?not used. aw29 rdw_synco_3 o receive dwac channel 3 drop superframe sync. ? quad 2.5 gbits/s mode?fec/dw drop superframe sync (~81.68/~20.42 khz) ? . ? 10 gbits/s mode?not used. aw30 rdw_datao_3 o receive dwac channel 3 drop data. ? quad 2.5 gbits/s mode?fec/dw drop data (~10.455 mbits/s) ? . ? 10 gbits/s mode?fec/dw drop data bit 3 of 4 (~10.455 mbits/s) ? . av30 rdw_clko_4 o receive dwac channel 4 drop clock. ? quad 2.5 gbits/s mode?fec/dw drop clock (~10.455 mhz) ? . ? 10 gbits/s mode?fec/dw not used. aw31 rdw_synco_4 o receive dwac channel 3 drop superframe sync. ? quad 2.5 gbits/s mode?fec/dw drop superframe sync (~81.68/~20.42 khz) ? . ? 10 gbits/s mode?not used. av31 rdw_datao_4 o receive dwac channel 4 drop data. ? quad 2.5 gbits/s mode?fec/dw drop data (~10.455 mbits/s) ? . ? 10 gbits/s mode?fec/dw drop data bit 4 of 4 msb (~10.455 mbits/s) ? .
36 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 15. pin descriptions?transmit digital wrapper overhead insert interface pin symbol type * * o = output, id = input with internal pull-down resistor. all i/o are 5 v compatible, 3.3 v ttl. they will tolerate 5 v at their i nputs or outputs. the value of all internal pull-down resistors is 50 k ? . ? the frequencies in the parenthesis are the fec rate and dw rate, respectively. name/description a27 tdw_clko_1 o transmit dwac (fec/dw) channel 1 insert clock. ? quad 2.5 gbits/s mode?fec/dw insert clock (~10.455/~10.455 mhz) ? . ? 10 gbits/s mode?fec/dw insert clock (~10.455/~10.455 mhz) ? . b27 tdw_synco_1 o transmit dwac (fec/dw) channel 1 insert superframe sync. ? quad 2.5 gbits/s mode?fec/dw insert superframe sync (~81.68/~20.42 khz) ? . ? 10 gbits/s mode?fec/dw insert superframe sync (~326.7/~81.68 khz) ? . c27 tdw_deni_1 id transmit dwac (fec/dw) channel 1 insert enable. ? quad 2.5 gbits/s mode?fec/dw insert enable. ? 10 gbits/s mode?fec/dw insert enable. d27 tdw_datai_1 id transmit dwac (fec/dw) channel 1 insert data. ? quad 2.5 gbits/s mode?fec/dw insert data (~10.455 mbits/s). ? 10 gbits/s mode?fec/dw insert data bit 1 of 4 (lsb) (~10.455 mbits/s). e27 tdw_clko_2 o transmit dwac (fec/dw) channel 2 insert clock. ? quad 2.5 gbits/s mode?fec/dw insert clock (~10.455 mhz). ? 10 gbits/s mode?not used. c28 tdw_synco_2 o transmit dwac (fec/dw) channel 2 insert superframe sync. ? quad 2.5 gbits/s mode?fec/dw insert superframe sync (~81.68/~20.42 khz) ? . ? 10 gbits/s mode?not used . d28 tdw_deni_2 id transmit dwac (fec/dw) channel 2 insert enable. ? quad 2.5 gbits/s mode?fec/dw insert enable. ? 10 gbits/s mode?not used. a29 tdw_datai_2 id transmit dwac (fec/dw) channel 2 insert data. ? quad 2.5 gbits/s mode?fec/dw insert data (~10.455 mhz). ? 10 gbits/s mode?fec/dw insert data bit 2 of 4 (~10.455 mbits/s). a30 tdw_clko_3 o transmit dwac (fec/dw) channel 3 insert clock. ? quad 2.5 gbits/s mode?fec/dw insert clock (~10.455 mhz). ? 10 gbits/s mode?not used. b30 tdw_synco_3 o transmit dwac (fec/dw) channel 3 insert superframe sync. ? quad 2.5 gbits/s mode?fec/dw insert superframe sync (~81.68/~20.42 khz) ? . ? 10 gbits/s mode?not used. e28 tdw_deni_3 id transmit dwac (fec/dw) channel 3 insert enable. ? quad 2.5 gbits/s mode?fec/dw insert enable. ? 10 gbits/s mode?not used. f28 tdw_datai_3 id transmit dwac (fec/dw) channel 3 insert data. ? quad 2.5 gbits/s mode?fec/dw insert data (~10.455 mbits/s). ? 10 gbits/s mode?fec/dw insert data bit 3 of 4 (~10.455 mbits/s). a31 tdw_clko_4 o transmit dwac (fec/dw) channel 4 insert clock. ? quad 2.5 gbits/s mode?fec/dw insert clock (~10.455 mhz). ? 10 gbits/s mode?not used. b31 tdw_synco_4 o transmit dwac (fec/dw) channel 4 insert superframe sync. ? quad 2.5 gbits/s mode?fec/dw insert superframe sync (~81.68/~20.42 khz) ? . ? 10 gbits/s mode?not used. c30 tdw_deni_4 id transmit dwac (fec/dw) channel 4 insert enable. ? quad 2.5 gbits/s mode?fec/dw insert enable. ? 10 gbits/s mode?not used. d30 tdw_datai_4 id transmit dwac (fec/dw) channel 4 insert data. ? quad 2.5 gbits/s mode?fec/dw insert data (~10.455 mbits/s). ? 10 gbits/s mode?fec/dw insert data bit 4 of 4 msb (~10.455 mbits/s).
agere systems inc. 37 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 16. pin descriptions?microprocessor interface pin symbol type * * i = input, o = output. all i/o are 5 v compatible, 3.3 v ttl. they will tolerate 5 v at their inputs or outputs. ? input with 50 k ? pull-up resistor. name/description a22 pclk i microprocessor clock. this clock can operate from 10 mhz to 78 mhz in asynchronous mode and 10 mhz to 50 mhz in synchronous mode. c21 cs_n i chip select (active-low). this signal must be low during register access. c19 ts_n i transfer start or address strobe (active-low). transfer start when mpmode = 1 (synchronous). address strobe when mpmode = 0 (asynchronous). d19 ds_n i ? data strobe (active-low). this signal, when used in the asynchronous mode (mpmode = 0), indicates that the data is valid for mpu writes. d21 rw_n i ? read/write . this signal is low to indicate a write operation and is high to indicate a read operation. d22 ta_n o data transfer acknowledge (active-low). this signal acknowledges the data transfer cycle. e22 tea_n o transfer error acknowledge (active-low). this signal goes low to indi- cate an internal error related to the data transfer cycle. f22 intl_n o interrupt low (active-low). this signal goes low when the device gener- ates an unmasked low-priority interrupt. the interrupt signal is cleared when the unmasked raw alarm that generated the interrupt is cleared. b22 inth_n o interrupt high (active-low). this signal goes low when the device gener- ates an unmasked high-priority interrupt. the interrupt signal is cleared when the unmasked raw alarm that generated the interrupt is cleared. b15 address_15 i ? address bus [15:0]. this bus is used to address registers. note: address_15 is the msb, address_0 is the lsb. a15 address_14 i ? d16 address_13 i ? c16 address_12 i ? b16 address_11 i ? a16 address_10 i ? f17 address_9 i ? e17 address_8 i ? b17 address_7 i ? a17 address_6 i ? f18 address_5 i ? e18 address_4 i ? d18 address_3 i ? c18 address_2 i ? b18 address_1 i ? a18 address_0 i ?
38 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 16. pin descriptions?microprocessor interface (continued) table 17. data bus and parity bit usage?8-bit and 16-bit modes pin symbol type * * i = input, o = output, i u = input with internal pull-up resistor. i/o are 5 v compatible, 3.3 v ttl. they will tolerate 5 v at their inputs or outputs. the value of all internal pull-up resistors is 100 k ? . ? input with 50 k ? pull-up resistor. name/description b26 data_15 i ? /o data bus [15:0]. this bus is a bidirectional data bus for writing and reading software registers. note: data_15 is the msb, data_0 is the lsb. a26 data_14 i ? /o d25 data_13 i ? /o c25 data_12 i ? /o f24 data_11 i ? /o e24 data_10 i ? /o b25 data_9 i ? /o a25 data_8 i ? /o d24 data_7 i ? /o c24 data_6 i ? /o b24 data_5 i ? /o a24 data_4 i ? /o f23 data_3 i ? /o e23 data_2 i ? /o b23 data_1 i ? /o a23 data_0 i ? /o f25 parity_0 i ? /o data bus parity?lower byte. odd parity for lower byte [7:0]. e25 parity_1 i ? /o data bus parity?upper byte. odd parity for upper byte [15:8]. mpdb_8_16 (pin d22) data bus size msb (bit) lsb (bit) parity bus 1 16 bits data_15 data_0 parity_1 and parity_0. 0 8 bits data_7 data_0 parity_0 only.
agere systems inc. 39 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 18. pin descriptions?jtag interface/scan signals pin symbol type * * i = input, o = output, i d = input with internal pull-down resistor (50 k ? ), i u = input with internal pull-up resistor (100 k ? ). i/o are 5 v compati- ble, 3.3 v ttl. they will tolerate 5 v at their inputs or outputs. name/description ar10 tck i d test clock. this signal provides timing for test operations. av7 tms i u test mode select. controls test operations. tms is sampled on the rising edge of tck. ap10 tdi i u test data in. tdi is sampled on the rising edge of tck. aw6 tdo o test data out. this output is updated on the falling edge of tck. the tdo output is 3-stated except when scanning out test data. aw7 trst_n i u test reset (active-low). this signal provides an asynchronous reset for the tap. this input should be tied low (to v ss ) for normal device operation. if trst_n is high, a tck must be present to ensure that the correct test mode is clocked in on the tms input. factory test e29 testmode i d scan testmode. active-high. no connect on operating designs. av34 scanclk1 i d scan clock 1. no connect on operating designs. aw34 scanclk2 i d scan clock 2. no connect on operating designs.
40 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 19. pin descriptions?gpio pin symbol type * name/description usage k6 gpio_1 i u /o gpio?general purpose i/o. available for internal uses. see the operational description for details. j4 gpio_2 i u /o gpio?general purpose i/o. j3 gpio_3 i u /o gpio?general purpose i/o. b35 gpio_4 i u /o gpio?general purpose i/o. a35 gpio_5 i u /o gpio?general purpose i/o. d33 gpio_6 i u /o gpio?general purpose i/o. c33 gpio_7 i u /o gpio?general purpose i/o. f31 gpio_8 i u /o gpio?general purpose i/o. e31 gpio_9 i u /o gpio?general purpose i/o. b33 gpio_10 i u /o gpio?general purpose i/o. a33 gpio_11 i u /o gpio?general purpose i/o. f30 gpio_12 i u /o gpio?general purpose i/o. e30 gpio_13 i u /o gpio?general purpose i/o. d31 gpio_14 i u /o gpio?general purpose i/o. c31 gpio_15 i u /o gpio?general purpose i/o. b32 gpio_16 i u /o gpio?general purpose i/o. a32 gpio_17 i u /o gpio?general purpose i/o. ap8 gpio_18 i u /o gpio?general purpose i/o. ar8 gpio_19 i u /o gpio?general purpose i/o. av5 gpio_20 i u /o gpio?general purpose i/o. aw5 gpio_21 i u /o gpio?general purpose i/o. ap9 gpio_22 i u /o gpio?general purpose i/o. ar9 gpio_23 i u /o gpio?general purpose i/o. av6 gpio_24 i u /o gpio?general purpose i/o. ap15 gpio_25 i u /o gpio?general purpose i/o. ar15 gpio_26 i u /o gpio?general purpose i/o. av14 gpio_27 i u /o gpio?general purpose i/o. aw14 gpio_28 i u /o gpio?general purpose i/o. at15 gpio_29 i u /o gpio?general purpose i/o. 1. i/o = bidirectional pin, i u = input with internal pull-up resistor. i/o are 5 v compatible, 3.3 v ttl. they will tolerate 5 v at their inputs or out- puts. the value of the internal pull-up resistors is 100 k ? .
agere systems inc. 41 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface au15 gpio_30 i u /o gpio?general purpose i/o. available for generic use. see the operational description for details. ap16 gpio_31 i u /o gpio?general purpose i/o. ar16 gpio_32 i u /o gpio?general purpose i/o. av15 gpio_33 i u /o gpio?general purpose i/o. aw15 gpio_34 i u /o gpio?general purpose i/o. av16 gpio_35 i u /o gpio?general purpose i/o. aw16 gpio_36 i u /o gpio?general purpose i/o. ap17 gpio_37 i u /o gpio?general purpose i/o. ar17 gpio_38 i u /o gpio?general purpose i/o. av17 gpio_39 i u /o gpio?general purpose i/o. aw17 gpio_40 i u /o gpio?general purpose i/o. ap18 gpio_41 i u /o gpio?general purpose i/o. ar18 gpio_42 i u /o gpio?general purpose i/o. at18 gpio_43 i u /o gpio?general purpose i/o. au18 gpio_44 i u /o gpio?general purpose i/o. at19 gpio_45 i u /o gpio?general purpose i/o. au19 gpio_46 i u /o gpio?general purpose i/o. aw22 gpio_47 i u /o gpio?general purpose i/o. av22 gpio_48 i u /o gpio?general purpose i/o. * i/o = bidirectional pin, i u = input with internal pull-up resistor. i/o are 5 v compatible, 3.3 v ttl. they will tolerate 5 v at their inputs or out- puts. the value of the internal pull-up resistors is 100 k ? . 2 pin information (continued) 2.2 pin descriptions (continued) table 19. pin descriptions?gpio (continued) pin symbol type * name/description usage
42 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 20. pin descriptions?power and ground pin symbol type * name/description a1, a2, a20, a38, a39, ac5, ac37, af4, af36, aj3, aj37, am4, am36, at8, at14, at20, at26, at32, au11, au17, au20, au23, au29, av1, av2, av20, av38, av39, aw1, aw2, aw20, aw38, aw39, b1, b2, b20, b38, b39, c11, c17, c20, c23, c29, d8, d14, d20, d26, d32, h4, h36, l4, l35, l37, p4, p36, u4, y1, y2, y3, y4, y36, y37, y38, y39 vdd p 3.3 v positive supply voltage (~3.15 w worst case). e5, e6, e19, e20, e21, e34, e35, f5, f6, f19, f20, f21, f34, f35, w5, w6, w34, w35, y5, y6, y34, y35, aa5, aa6, aa34, aa35, ap5, ap6, ap19, ap20, ap21, ap34, ap35, ar5, ar6, ar19, ar20, ar21, ar34, ar35 vdd15 p 1.5 v positive supply voltage (~3.15 w worst case). a19, a21, aa1, aa2, aa38, aa39, ac36, ac6, af3, af37, aj4, aj36, am3, am37, at3, at4, at11, at17, at23, at29, at36, at37, au3, au4, au8, au14, au26, au32, au36, au37, av19, av21, aw19, aw21, b19, b21, c3, c4, c8, c14, c26, c32, c36, c37, d3, d4, d11, d17, d23, d29, d36, d37, h3, h37, l3, l34, l36, p3, p37, u3, w1, w2, w38, w39 vss g ground. 1. p = power, g = ground.
agere systems inc. 43 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface w3, v35, t38, t1, r5, r3, m5, k5, j35, j34, h6, h5, h35, h34, h2, h1, g6, g5, g37, g36, g35, g34, f7, f4, f37, f36, f33, f32, f3, f29, f27, f26, f16, f12, e7, e4, e39, e38, e37, e36, e33, e32, e3, e26, e2, e16, e12, e1, d5, d39, d38, d35, d34, d2, d1, c5, c39, c38, c35, c34, c2, c1, aw4, aw37, aw35, aw33, aw32, aw3, aw27, aw26, aw25, aw24, aw23, aw18, aw13, aw11, av4, av37, av35, av33, av32, av3, av29, av27, av26, av25, av24, av23, av18, av13, av11, au7, au6, au5, au39, au38, au35, au33, au31, au30, au25, au24, au21, au2, au16, au1, at7, at6, at5, at39, at38, at35, at33, at31, at30, at28, at27, at25, at24, at21, at2, at16, at1, ar7, ar4, ar39, ar38, ar37, ar36, ar30, ar3, ar29, ar28, ar27, ar24, ar23, ar22, ar2, ar1, ap7, ap4, ap37, ap36, ap30, ap3, ap29, ap28, ap27, ap26, ap24, ap23, ap22, an6, an5, an38, an35, an34, am6, am5, am35, am34, al34, ak36, aj6, aj5, ag37, ag35, ae6, ae39, ad6, ab6, ab34, aa37, a4, a37, a36, a34, a3, a28, a14, a11, b3, b4, b6, b8, b9, b11, b12, b14, b28, b29, b34, b36, b37 nc ? no connect. do not connect these pins. * p = power, g = ground. 2 pin information (continued) 2.2 pin descriptions (continued) table 20. pin descriptions?power and ground (continued) pin symbol type * name/description
44 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 2 pin information (continued) 2.2 pin descriptions (continued) table 21. pin count summary note: cmos inputs are 5 v tolerant. logic inputs can be driven from standard ttl levels, and logic outputs can drive stan- dard ttl inputs. 3.3 v ttl is preferred. interface pin count system control pins 7 transmit phase detectors 8 receive phase detectors 8 receive line interface 48 receive line interface lvds reference 16 receive system interface 48 transmit system interface 40 transmit system/line lvds reference 16 lvds reference 4 transmit line interface 56 receive section/line oh (drop) 24 transmit section/line oh (insert) 28 receive fec/dw oh drop 12 transmit dw oh insert 16 microprocessor interface 43 jtag/scan 8 gpio 48 interface pins 430 power (3.3 v supply) 64 power (1.5 v supply) 40 ground 64 no connect 194 total 792
agere systems inc. 45 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 3 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. component case temperature shall not exceed 220 c during solder reflow attachment. table 22. absolute maximum ratings 4 typical operating conditions table 23. recommended operating conditions 5 thermal characteristics table 24. 792-pin pbgam thermal resistance note: any heat sink that has a lower thermal specification than those specified in table 24 is adequate for use with the device. table 25. package temperature coefficients (without heat sink) parameter symbol min max unit storage temperature t stg ?65 125 c voltage on any pin with respect to ground v ss gnd ? 0.5 v dd + 0.5* * this maximum rating only applies when the device is powered up with v dd . v power dissipation p d ?6.3w parameter symbol min typ max unit power supply?3.3 v i/o v dd 3.135 3.3 3.465 v power supply?1.5 v v dd 1.425 1.5 1.575 v low-level input voltage v il see table 27, logic interface characteristics, on page 46. v high-level input voltage v ih v ambient operating temperature range t a ?40 ? 85 c power (w) thermal budget (c/w) (theta-jc) (c/w) heat sink speck (c/w) theta-ja (c/w) theta-ja with airflow (200 linear feet per minute) (c/w) 6 6.7 2.2 4.5 14.5 11.5 parameter symbol value airflow junction to ambient ja 10.5 c/w 0 linear meters/second junction to ambient ja 8.5 c/w 100 linear meters/second junction to ambient ja 7.5 c/w 250 linear meters/second
46 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 6 handling precautions although electrostatic discharge (esd) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to esd and electrical overstress (eos) during all handling, assembly, and test operations. agere employs both a human-body model (hbm) and a charged-device model (cdm) qualification requirement in order to determine esd-susceptibility limits and protection design evaluation. esd voltage thresh- olds are dependent on the circuit parameters used in each of the models, as defined by jedec's jesd22-a114 (hbm) and jesd22-c101 (cdm) standards. table 26. hbm esd minimum threshold 7 electrical characteristics table 27. logic interface characteristics figure 2. generic interface data timing device model voltage tfec0410g minimum hbm threshold 2000 v minimum cdm 500 v parameter symbol test conditions min max unit input voltage: low high v il v ih ? gnd v dd ? 1.0 1.0 v dd v v input leakage i l ??1.0 a output voltage: low high v ol v oh ?5.0 ma 5.0 ma gnd v dd ? 1.0 0.5 v dd v v input capacitance c i ? ? ?pf load capacitance c l ?? ?pf clock data clock data t su t h t pd
agere systems inc. 47 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 7 electrical characteristics (continued) 7.1 low-voltage differential signal (lvds) buffers the lvds buffers are compliant with the eia ? -644 standard. the only exception to compliance with this standard is associated with the input leakage current. the lvds input buffers have a maximum input leakage current of 300 a. the lvds buffers are also compliant to the ieee ? 1596.3 standard. the only exception to compliance with this standard is the input termination resistance. the lvds input buffers have an input termination resistance of 100 ? 20%. the lvds outputs are hot-swap compatible, and can be connected to other vendor?s lvds i/o buffers. the maxi- mum input current for the agere systems inc. lvds input buffers is 9 ma. prolonged exposure to higher current levels will have an impact on long-term reliability. the lvds buffers support point-to-point connections. they are not intended for, and are not recommended for, bussed implementations. unused lvds inputs may be left unconnected. they have circuitry that forces them to remain in a defined state if left open. open inputs will not oscillate for this reason. unused lvds inputs may be left unconnected. they have 14 k ? 40% pull-up resistors that forces them to remain in a defined state if left open. open inputs will not oscillate for this reason. figure 3. lvds driver and receiver and associated internal components figure 4. lvds driver and receiver lvds driver 50 ? 50 ? lvds receiver center tap device pins 100 ? external v gpd v oa v ob v ia v ib a b aa bb driver interconnect receiver
48 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 7 electrical characteristics (continued) 7.1 low-voltage differential signal (lvds) buffers (continued) figure 5. lvds driver 7.1.1 lvds receiver buffer capabilities a disabled or unpowered lvds receiver can withstand a driving lvds transmitter over the full range of driver oper- ating range, for an unlimited period of time, without being damaged. table 28 illustrates lvds driver dc data, table 29 the ac data, and table 31 on page 49 the lvds receiver data. note: v dd = 3.1 v?3.5 v, 0 c?125 c, slow-fast process. table 28. lvds driver dc data parameter symbol conditions min typ max unit driver output voltage high, v oa or v ob v oh r load = 100 ? 1% refer to figure 5 on page 48. ? ? 1.475* * external reference, ref10 = 1.0 v 3%, ref14 = 1.4 v 3%. see figure 1 on page 27 for a schematic. v driver output voltage low, v oa or v ob v ol r load = 100 ? 1%. 0.925* ? ? v driver output differential voltage v od = (v oa ? v ob ) (with external reference resistor) ? v od ? r load = 100 ? 1%. 0.25 ? 0.45* v driver output offset voltage v os = (v oa + v ob )/2 v os r load = 100 ? 1% refer to figure 5 on page 48. 1.125* ? 1.275* v output impedance, single-ended r o v cm = 1.0 v and 1.4 v. 40 50 60 w r o mismatch between a and b ? ! r o v cm = 1.0 v and 1.4 v. ? ? 10 % change in ?? ! v od ? between 0 and 1 ?? ! v od ? r load = 100 ? 1%. ? ? 25 mv change in ?? ! v os ? between 0 and 1 ?? ! v os ? r load = 100 ? 1%. ? ? 25 mv output current i sa, i sb driver shorted to ground. ? ? 24 ma output current i sab driver shorted together. ? ? 12 ma power-off output leakage ? i xa ? , ? i xb ? v dd = 0 v. v pad , v padn = 0 v?3 v. ??30 a v oa a v ob b c a c b r load v od = (v oa ? v ob ) v
agere systems inc. 49 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 7 electrical characteristics (continued) 7.1 low-voltage differential signal (lvds) buffers (continued) table 29. lvds driver ac data table 30. lvds driver reference data table 31. lvds receiver dc data table 32. lvds receiver ac data parameter symbol conditions min max unit v od fall time, 80% to 20% tfall z load = 100 ? 1%. c pad = 3.0 pf, c padn = 3.0 pf. 100 210 ps v od rise time, 20% to 80% trise z load = 100 ? 1%. c pad = 3.0 pf, c padn = 3.0 pf. 100 210 ps differential skew ? tp hla ? tp lhb ? or ? tp hlb ? tp lha ? tskew1 any differential pair on package at 50% point of the transition. ?50ps parameter conditions min typ max unit ref10e, ref10l voltage range ? 0.95 1.0 1.05 v ref14e, ref14l voltage range ? 1.35 1.4 1.45 v nominal input current?ref10 and ref14 reference inputs ??10? a parameter symbol conditions min typ max unit receiver input voltage range, v ia or v ib v i ? v gpd ? < 925 mv dc?1mhz. 0 1.2 2.4 v receiver input differential threshold ? v idth ?? v gpd ? < 925 mv?400 mhz. ?100 ? 100 mv receiver input differential hysteresis v hyst v idthh ? v idthl .???* * buffer will not produce transition when input is open-circuited. mv receiver differential input impedance r in with built-in termination, center tapped. 80 100 120 w parameter symbol conditions min typ max unit output rise time (20%?80%) tr cl = 0.5 pf. 150 ? 350 ps output fall time (80%?20%) tf cl = 0.5 pf. 150 ? 350 ps
50 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 8power 8.1 power sequencing the device power should be applied concurrently to both voltage level inputs. the 3.3 v supply powers the i/o buff- ers, and the 1.5 v supply powers the core logic of the device. in the event that either supply is powered individually, even for a reasonably long period of time (such as a few seconds), the device will not be damaged. in the event both voltages are not applied concurrently, a device reset is recommended before normal operation. 8.2 power consumption the following table (table 26) lists the maximum power consumption (by mode) of the tfec0410g device. table 33. tfec0410g power consumption mode power consumption strong fec/digital wrapper?terminal 10 gbits/s tbd quad 2.5 gbits/s tbd dual 2.5 gbits/s tbd single 2.5 gbits/s tbd strong fec/digital wrapper?regenerator 10 gbits/s tbd quad 2.5 gbits/s tbd strong fec/digital wrapper?bidirectional mode 10 gbits/s tbd quad 2.5 gbits/s tbd weak fec?terminal 10 gbits/s tbd quad 2.5 gbits/s tbd weak fec?regenerator 10 gbits/s tbd quad 2.5 gbits/s tbd strong (digital wrapper) fec/weak fec?terminal 10 gbits/s tbd quad 2.5 gbits/s tbd
agere systems inc. 51 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 9 timing characteristics 9.1 receive/transmit input data/sync interface 9.1.1 receive (line)/transmit (system) quad 2.5 gbits/s mode/10 gbits/s mode data and sync inputs figure 6 illustrates the timing for the receive (line) and transmit (system) quad 2.5 gbits/s/10 gbits/s data stream. both the clock and data pins are low-voltage differential signal (lvds) input buffers. the expected clock rate is 622.08 mhz?692.64 mhz and the receive/transmit data is clocked on the rising edge of the clock. in quad 2.5 gbits/s mode, each channel uses one set of rclkli_[15?0]/tclksi_[15?0] and rdli_[4?1]_[3:0]/ tdsi_[4?1]_[3:0] data pins. in 10 gbits/s mode, or virtual 10 gbits/s mode (data is arranged as four 2.5 gbits/s signals), only rclkli_1/tclksi_1 are used, along with the 16 rdli/tdsi pins, respectively. both the clock and frame sync are low-voltage differential signal (lvds) input buffers. the expected clock is 666.51 mhz?692.64 mhz and the sync is clocked on the rising edge of the clock. in quad 2.5 gbits/s mode, each channel uses one set of tclkli_[4?1] and tfrmli_[4?1] sync pins. in 10 gbits/s mode, only tclkli_1 is used, along with the tfrmli_1 sync input. the timing values for the diagram are given in table 34. figure 6. receive/transmit data timing table 34. receive (line)/transmit (system) data timing symbol parameter min typ max unit t1 clock period ? 1608/1443 ? ps t2 data setup time required 220 ? ? ps t3 data hold time required 220 ? ? ps rclkli_[4?1], rdli_[4?1][3:0], n p p n t1 t3 t2 tclksi_[4?1], tclkli_[4?1] tdsi_[4?1][3:0] tfrmli_[4?1]
52 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 9 timing characteristics (continued) 9.1 receive/transmit input data/sync interface (continued) 9.1.2 transmit (line)/receive (system) quad 2.5 gbits/s/10 gbits/s data outputs figure 7 illustrates the timing for the transmit (line)/receive (system) quad 2.5 gbits/s/10 gbits/s output data streams. both the clock and data pins are driven with low-voltage differential signal buffers. the expected clock rate is 622.08 mhz?692.64 mhz and the receive/transmit data is clocked out on the rising edge of the clock. in quad 2.5 gbits/s mode, each channel uses one set of rclkso_[4?1]/tclklo_[4?1] and rdso_[4?1]_[3:0]/ tdlo_[4?1]_[3:0] data pins. in 10 gbits/s mode, or virtual 10 gbits/s mode (data is arranged as four 2.5 gbits/s signals), only rclkso_1/tclklo_1 are used, along with the 16 rdso/tdlo pins respectively. the timing val- ues for the diagram are given in table 35. figure 7. transmit (line)/receive (system) data timing table 35. transmit (line)/receive (system) data output timing 9.1.3 receive transport overhead access channel (rtoac) 9.1.3.1 full toac drop mode (rx) the rtoac_data_[4?1]_[3:0] pins transmit the complete transport overhead data for every received frame. the rtoac_data_[4?1]_ [3:0] pins are timed using the rising edge of the ttoac_clko_[4?1] signal. sam- pling of the rtoac_datao_[4?1]_[3:0] pins is intended to occur at the positive edge of the rtoac_clko_[4?1] signals. 1296 overhead bytes are transmitted in 125 s using a 4-bit interface, making the average frequency of rtoac_clk 20.736 mhz. the rtoac_synco_[4?1] pins indicate the frame position by toggling high during the most significant nibble of the first a1 byte in the data stream, as illustrated in figure 8 on page 53. symbol parameter min typ max unit t4 clock period ? 1608/1443 ? ps ? duty cycle* * this requirement is for all sources of the output clocks (e.g., rclksi, etc.). 45 50 55 % t5 data delay from clock edge ?220 ? 220 ps t6 data rise time: 20%?80% 100 ? 200 ps t7 data fall time: 80%?20% 100 ? 200 ps ? clock output variation ? 3 bit periods at 622.08 mhz ?? t5 tdlo_[4?1][3:0], p n n p t6, t7 tclklo, t4 rclkso rdso_[4?1][3:0]
agere systems inc. 53 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 9 timing characteristics (continued) 9.1 receive/transmit input data/sync interface (continued) 9.1.3.2 partial (first sts-1) toac drop mode (rx) the rtoac_datao_[4?1]_0 pin transmits the first sts-1 transport overhead data for every received frame. the rtoac_datao_[4?1]_ 0 pin is timed using the rising edge of the rtoac_clko_[4?1] signal. sampling of the rtoac_datao_[4?1]_0 pin is intended to occur at the positive edge of the rtoac_clk_[4?1] signals. 27 overhead bytes are transmitted in 125 s using a 1-bit interface, making the average frequency of rtoac_clk 1.728 mhz. the rtoac_synco_[4?1] pin indicates the frame position by toggling high during the most significant bit of the first a1 byte in the data stream, as illustrated in figure 8. the timing characteristics for the receive overhead serial pins are given in figure 8 and table 36. figure 8. receive overhead serial timing (drop) table 36. receive transport overhead access channel timing (full toac drop mode?20.736 mhz) symbol parameter min typ max unit t13 clock period (long clock) ? 51.44 ? ns t14 clock high width ? 25.72 ? ns t15 clock period (short clock) ? 38.58 ? ns t16 clock low width ? 12.86 ? ns t17 clock to data delay 0.6 ? 8 ns t18 clock to frame pulse delay 0.6 ? 8 ns t14 t17 rtoac_clk_[4?1] rtoac_datao_[4?1] rtoac_synco_[4?1] oa1 [7]/oa1 [7:4] oa1 [6]/... oa1 [5]/... oa1 [4]/... oa1... t18 msb/n t13 t16 t15
54 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 9 timing characteristics (continued) 9.1 receive/transmit input data/sync interface (continued) table 37. receive transport overhead access channel timing (sts-1 toac drop mode?1.728 mhz) table 38. receive transport overhead access channel timing?load/rise and fall times symbol parameter min typ max unit t13 clock period (long clock) ? 617.28 ? ns t14 clock high width ? 308.64 ? ns t15 clock period (short clock) ? 462.96 ? ns t16 clock low width ? 154.32 ? ns t17 clock to data delay 0.6 ? 8 ns t18 clock to frame pulse delay 0.6 ? 8 ns signal test load max?tr/tf unit rtoac_clko_[4?1] c l = 15 pf 3.5/3.5 ns rtoac_datao_[4?1]_[3:0] c l = 15 pf 3.5/3.5 ns rtoac_synco_[4?1] c l = 15 pf 3.5/3.5 ns
agere systems inc. 55 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 9 timing characteristics (continued) 9.1 receive/transmit input data/sync interface (continued) 9.1.4 transmit transport overhead access channel figure 9. transmit overhead serial timing 9.1.4.1 full toac drop mode (tx) the ttoac_datai_[4?1]_[3:0] pins are optionally used to insert transport overhead bytes into the transmit data stream. the ttoac_datai_[4?1]_[3:0] pins are sampled internally using the rising edge of the ttoac_clko_[4?1] signal. generation of the ttoac_datai signal is intended to occur at the positive edge of the ttoac_clko signal. this is possible since there is zero hold time required on the ttoac_datai_[4?1]_[3:0] inputs. 1296 overhead bytes are received in 125 s using a 4-bit interface, which makes the average frequency of ttoac_clko 20.736 mhz. the ttoac_synco_[4?1] pin indicates the frame position by toggling high during the most significant nibble of the first a1 byte in the data stream, as illustrated in figure 9. the timing characteristics for the transmit overhead serial pins are given in table 39 on page 56. ttoac_deni_[4?1] is only sampled on the rising edge of the clock during the most significant nibble and least significant nibble of the byte (see figure 9). ttoac_clk[4?1] ttoac_datai_[4?1]_[3:0] ttoac_synco_[4?1] a1 [7:4] a1 [3:0] a1 [7:4] a1 [3:0] a1 . . . t36 ...e2 t32 lsn msn ttoac_deni_[4?1] t29 t33 t31 t30 t30 t34 t35
56 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 9 timing characteristics (continued) 9.1 receive/transmit input data/sync interface (continued) 9.1.4.2 partial (first sts-1) toac drop mode (tx) the ttoac_datai_[4?1]_0 pin is optionally used to insert transport overhead bytes into the transmit data stream. the ttoac_datai_[4?1]_0 pin is sampled internally using the rising edge of the ttoac_clko_[4?1] signal. generation of the ttoac_datai signal is intended to occur at the positive edge of the ttoac_clk signal. this is possible since there is zero hold time required on the ttoac_datai_[4?1]_[3:0] inputs. 27 overhead bytes are received in 125 s using a 1-bit interface, which makes the average frequency of ttoac_clk 1.728 mhz. the ttoac_synco_[4?1] pin indicates the frame position by toggling high during the most significant bit of the first a1 byte in the data stream, as illustrated in figure 9 on page 55. the timing characteristics for the transmit overhead serial pins are given in table 40 on page 57. ttoac_deni_[4?1] is sampled on the rising edge of the clock during the most significant bit [7] and bit [6] of the byte (see figure 9 on page 55). table 39. transmit transport overhead access channel timing (full toac mode?20.736 mhz) symbol parameter min typ max unit t29 clock period (long clock) ? 51.44 ? ns t30 clock low width ? 25.72 ? ns t31 clock period (short clock) ? 38.58 ? ns t32 data setup time required 8 ? ? ns t33 data hold time required 0 ? ? ns t34 ttoac_deni_[4?1] setup time required 8 ? ? ns t35 ttoac_deni_[4?1] hold time required 0 ? ? ns t36 clock to frame pulse delay* * the frame pulse may occur after either a long clock or a short clock. 0.6 ? 8 ns
agere systems inc. 57 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 9 timing characteristics (continued) 9.1 receive/transmit input data/sync interface (continued) table 40. transmit transport overhead access channel timing (partial (sts-1) toac mode?1.728 mhz) table 41. transmit transport overhead access channel?load/rise and fall times 9.1.5 receive fec/digital wrapper receive overhead drop interface the rdw_datao_[4?1] pin transmits the complete fec/dw overhead every received fec frame. the rdw_datao_[4?1] pins are timed using the rising edge of the rdw_clko_[4?1] signal. sampling of the rdw_datao_[4?1] pins is intended to occur at the positive edge of the rdw_clko_[4?1] signals. since 16 overhead bytes are transmitted per fec frame using a 1/4-bit interface, the average frequency of rdw_clko_[4?1] is 10.455 mhz in both 2.5 gbits/s and 10 gbits/s mode. the rdw_synco_[4?1] pin indicates the frame position by toggling high during the most significant bit/nibble of the first overhead byte in the data stream, as illustrated in figure 10 on page 58. the timing characteristics for the receive overhead serial pins are given in table 42 on page 58. symbol parameter min typ max unit t29 clock period (long clock) ? 617.28 ? ns t30 clock low width ? 308.64 ? ns t31 clock period (short clock) ? 462.96 ? ns t32 data setup time required 8 ? ? ns t33 data hold time required 0 ? ? ns t34 ttoac_deni_[4?1] setup time required 8 ? ? ns t35 ttoac_deni_[4?1] hold time required 0 ? ? ns t36 clock to frame pulse delay* * the frame pulse may occur after either a long clock or a short clock. 0.6 ? 8 ns signal test load max?tr/tf unit ttoac_clk_[4?1] c l = 15 pf 3.5/3.5 ns ttoac_synco_[4?1] c l = 15 pf 3.5/3.5 ns ttoac_datai_[4?1] na* * not applicable. no test load. 3.5/3.5 ns ttoac_deni_[4?1] na* 3.5/3.5 ns
58 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 9 timing characteristics (continued) 9.1 receive/transmit input data/sync interface (continued) figure 10. receive dw data communication channels timing table 42. receive dw data communication channels timing parameters table 43. receive dw data communication channels?load/rise and fall times 9.1.6 transmit fec/digital wrapper insert overhead channel the tdw_datai_[4?1] pins are optionally used to insert fec/digital wrapper (och) overhead bytes into the transmit data stream. the tdw_datai_[4?1] pins are sampled internally using the rising edge of the tdw_clko_[4?1] signal. generation of the tdw_datao_[4?1] signals are intended to occur at the positive edge of the tdw_clko signal. this is possible since there is zero hold time required on the tdw_datai_[4?1] inputs. 16 overhead bytes are received in one fec/dw frame period using a 1-bit interface, which makes the average fre- quency of tdw_clko_[4?1] 10.455 mhz. the tdw_synco_[4?1] pin indicates the frame position by toggling high during the most significant bit of the first overhead byte in the data stream, as illustrated in figure 11 on page 59. symbol parameter min typ max unit t53 clock period (long clock) ? 96.02 ? ns t54 clock high width ? 48.01 ? ns t55 clock period (short clock) ? 84.02 ? ns t56 clock low width ? 36.01 ? ns t57 clock to data delay 0.6 ? 8 ns t58 clock to frame pulse delay 0.6 ? 8 ns signal test load max?tr/tf unit rdw_clko_[4?1] c l = 15 pf 3.5/3.5 ns rdw_datao_[4?1] c l = 15 pf 3.5/3.5 ns rdw_synco_[4?1] c l = 15 pf 3.5/3.5 ns t54 t57 rdw_clko_[4?1] rdw_datao_[4?1] rdw_synco_[4?1] oa1 [7]/oa1 [7:4] oa1 [6]/ . . . oa1 [5]/ . . . oa1 [4]/ . . . oa1... t58 msb/n t53 t56 t55
agere systems inc. 59 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 9 timing characteristics (continued) 9.1 receive/transmit input data/sync interface (continued) the tdw_deni_[4?1] is an encoded signal sampled on the rising edge of the dwac clock which identifies three possible actions: the dwac data overwrites the selected overhead byte, a default value is inserted, or the incom- ing value is passed unchanged. the timing characteristics for the transmit overhead serial pins are given in figure 11 and table 44. figure 11. transmit fec/digital wrapper overhead serial timing table 44. transmit fec/digital wrapper overhead channel table 45. transmit fec/digital wrapper overhead channel?load/rise and fall times symbol parameter min typ max unit t59 clock period (long clock) ? 96.02 ? ns t60 clock high width ? 48.01 ? ns t61 clock period (short clock) ? 84.02 ? ns t62 clock low width ? 36.01 ? ns t63 data setup time required 8 ? ? ns t64 data hold time required 0 ? ? ns t65 tdw_deni_[4?1] setup time required 8 ? ? ns t66 tdw_deni_[4?1] hold time required 0 ? ? ns t67 clock to frame pulse delay 0.6 ? 8 ns signal test load max?tr/tf unit tdw_clko_[4?1] c l = 15 pf 3.5/3.5 ns tdw_synco_[4?1] c l = 15 pf 3.5/3.5 ns tdw_datai_[4?1] na 3.5/3.5 ns tdw_deni_[4?1] na 3.5/3.5 ns tdw_clko_[4?1] tdw_datai_[4?1] tdw_synco_[4?1] oa1[6], oa1[3:0] oa1[5], oa1[7:4] oa1 t67 t63 msb/n tdw_deni_[4?1] t65 t59 t64 t66 t61 t62 t60 lsn oa1[7], oa1[7:4]
60 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 10 test 10.1 scan this device supports the ieee 1149.1 jtag interface for memory bist, boundary scan, and 32-bit id register instructions. 10.2 boundary scan full boundary scan is supported on this device. boundary scan is activated from the jtag port. 10.3 ram bist embedded memories support bist. the bist algorithm is activated from the jtag port.
agere systems inc. 61 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 11 microprocessor interface 11.1 microprocessor interface overview the tfec0410g microprocessor interface architecture is configured for glueless interface to the motorola mpc860 and mc68360 microprocessors. the intel microcontrollers 8xc251 and 80c196 and the i960 micropro- cessor may also be utilized to interface to the tfec0410g. however, provisions on the board need to be made to (de)multiplex the address and data bus. the state of the mptype_im input signal indicates to the device whether it interfaces to a motorola microprocessor or an intel microcontroller. other microprocessors may be used if their timing requirements fit to one of the modes described. the tfec0410g has separate 16-bit wide address and data busses. the mpdb_8_16 input distinguishes between an 8-bit or 16-bit wide microprocessor data bus being used. in case of an 8-bit wide microprocessor data bus interface, the eight upper bits of the device data bus ports are not being used and are held 3-state. the microprocessor interface operates at the frequency of the microprocessor clock (pclk) input which should be in the range of 10 mhz to 100 mhz. depending on the state of the mpmode_as input signal, the interface to the 80960sx microprocessor is synchro- nous, while the interface to the 8xc251 and 80c196 microcontrollers is asynchronous. similarly, with the mpc860 or mc68360 microprocessors being used, the state of the mpmode_as input signal determines whether bus transfers are synchronous or asynchronous, respectively. in this case, the microprocessor interface also generates an external processor bus error if an internal data acknowledgment is not received in a predetermined period of time, or on parity errors if the mpparen input is enabled. all internal counters are latched using an external or internal performance monitor (pm) latch pulse that must occur once per second to ensure all internal counters do not saturate. persistency alarm registers are used in conjunction with the interrupt alarm registers to indicate whether alarms are persistent. the tfec0410g contains 48 general purpose inputs/outputs (gpios), which can be used to monitor signals on the board. 11.2 microprocessor interface modes table 46 highlights the four microprocessor modes controlled by the mptype_im and mpmode_as inputs. table 46. microprocessor configuration modes mode mptype_im mpmode_as description typical application mode 1 1 1 synchronous interface; handshake using data acknowledge. mpc860 mode 2 1 0 asynchronous interface; handshake using data acknowledge. mc68360, mc68hc16x mode 3 0 1 synchronous interface; handshake through inserted wait states; asynchronous address latching. i960 (80960sx) mode 4 0 0 asynchronous interface; handshake through inserted wait states; asynchronous address latching. 80c196, 8xc251
62 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 11 microprocessor interface (continued) 11.3 microprocessor interface timing the following sections show the timing specification of the external microprocessor interface in the four different modes. note that all output timings assume a 70 pf external load. 11.3.1 mode 1 (mpc860) the synchronous microprocessor interface mode for the mpc860 is selected when mptype_im = 1 and mpmode_as = 1. interface timing for the synchronous mode write cycle is given in figure 12 and in table 47. interface timing for the read cycle is given in figure 13 and table 49 on page 63. figure 12. microprocessor interface mode 1?write cycle timings table 47. microprocessor interface mode 1?write cycle timing specifications symbol parameter min max unit tc pclk period 20 100 ns tcycle bus transfer cycle time 5* * this value would be 35 tc in case of a transfer error (ta_n = 1, tea_n = 0). tc t101 cs_n, ts_n, rw_n asserted low setup to pclk rise 5 ? ns t102 address_n valid setup to pclk rise tc + 5 ? ns t103 data_n valid setup to pclk rise 7 ? ns t104 ts_n asserted low hold after pclk rise 0 ? ns t105 cs_n asserted low to ta_n/tea_n high delay ? 10 ns t106 pclk rise to ta_n/tea_n asserted low delay 2 10 ns t107 pclk rise to ta_n/tea_n negated high delay 2 10 ns t108 cs_n negated to ta_n/tea_n 3-state delay ? 10 ns t109 cs_n, rw_n asserted low hold/address_n, data_n valid hold after pclk rise 0?ns pclk address_n cs_n ts_n rw_n ta_n/tea_n data_n/parity_[1:0] (input) t101 t102 t105 t106 t107 t108 t109 high-z high-z t103 inserted wait-states valid valid t104 tcycle tc
agere systems inc. 63 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 11 microprocessor interface (continued) 11.3 microprocessor interface timing (continued) table 48. ta_n/tea_n cycle termination for mode 1?write cycle figure 13. microprocessor interface mode 1?read cycle timings table 49. microprocessor interface mode 1?read cycle timing specifications table 50. ta_n/tea_n cycle termination for mode 1?read cycle ta_n tea_n encoding description 0 0 write data parity error. 0 1 normal cycle termination. 1 0 access to undefined address region and bus time-out?transfer error. 1 1 no cycle termination?external processor generated time-out. symbol parameter min max unit tcycle bus transfer cycle time 7 16* * this value would be 35 tc in case of a transfer error (ta_n = 1, tea_n = 0). the typical value for most of the register accesses i s 8 tc. tc t110 pclk rise to data_n valid delay 2 16 ns t111 pclk rise to data_n 3-state delay 2 16 ns ta_n tea_n encoding description 0 0 not possible during read cycle. 0 1 normal cycle termination. 1 0 access to undefined address region and bus time-out?transfer error. 1 1 no cycle termination?external processor generated time-out. pclk address_n cs_n ts_n rw_n ta_n/tea_n data_n/parity_[1:0] (output) t101 t102 t105 t106 t107 t111 high-z high-z inserted wait-states valid t104 tcycle t110 t108
64 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 11 microprocessor interface (continued) 11.3 microprocessor interface timing (continued) 11.3.2 mode 2 (mc68360) the asynchronous microprocessor interface mode for the mc68360 is selected when mptype_im = 1 and mpmode_as = 0. interface timing for the asynchronous mode write cycle is given in figure 14 and in table 51. interface timing for the read cycle is given in figure 15 and in table 53. all microprocessor signals to the device should be stable for at least the time of one cycle of pclk plus additional setup time to be safely detected by the device. for this reason, the pclk should be connected to the clko2 out- put of the mc68360 or a faster clock. figure 14. microprocessor interface mode 2?write cycle timings table 51. microprocessor interface mode 2?write cycle timing specifications symbol parameter min max unit tc pclk period 10 100 ns t121 address_n valid setup to cs_n, ds_n, ts_n asserted low 0 ? ns t122 cs_n asserted low to ta_n/tea_n high delay ? 10 ns t123 rw_n asserted low setup to ts_n asserted low 0 ? ns t124 data_n valid setup to ds_n asserted low 0 ? ns t125 ds_n asserted low to ta_n/tea_n asserted low delay 5 6* * this value would be 36 tc in case of a transfer error (ta_n = 1, tea_n = 0). tc t126 cs_n, ds_n, ts_n asserted low hold after ta_n asserted low 1 ? tc t127 rw_n asserted low hold after ds_n negated 0 ? ns t128 data_n valid hold after ds_n negated 0 ? ns t129 address_n valid hold after ts_n negated 0 ? ns t130 ts_n negated to ta_n/tea_n asserted high delay 0 10 ns t131 cs_n negated to ta_n/tea_n 3-state delay ? 10 ns t132 ts_n negated hold after ts_n asserted tc + 5 ? ns address_n cs_n ts_n(as) ds_n rw_n data_n ta_n/tea_n (input) t124 t122 t125 t130 t131 t127 t121 high-z high-z t121 t126 t126 t126 t123 valid valid t128 t129 t121 t132
agere systems inc. 65 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 11 microprocessor interface (continued) 11.3 microprocessor interface timing (continued) table 52. ta_n/tea_n cycle termination for mode 2?write cycle figure 15. microprocessor interface mode 2?read cycle timings table 53. microprocessor interface mode 2?read cycle timing specifications table 54. ta_n/tea_n cycle termination for mode 2?read cycle mode 3 ( i960 ) ta_n tea_n encoding description 0 0 write data parity error. 0 1 normal cycle termination. 1 0 access to undefined address region and bus time-out?transfer error. 1 1 no cycle termination?external processor generated time-out. symbol parameter min max unit t133 ts_n (as) asserted low to ta_n/tea_n asserted low delay 7 22* * this value would be 36 tc in case of a transfer error (ta_n = 1, tea_n = 0). the typical value for most of the register access es is 8 tc. tc t134 ts_n (as) asserted low to data_n valid delay 6 21 tc t135 ts_n negated to data_n 3-state delay 0 16 ns ta_n tea_n encoding description 0 0 not possible during read cycle. 0 1 normal cycle termination. 1 0 access to undefined address region and bus time-out?transfer error. 1 1 no cycle termination?external processor generated time-out. address_n cs_n ts_n(as) rw_n ta_n/tea_n t132 t133 t130 t131 high-z high-z t121 t126 t126 t121 valid t29 data_n high-z high-z t134 t135 valid (output) t132 t129
66 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 11 microprocessor interface (continued) 11.3 microprocessor interface timing (continued) 11.3.3 mode 3 ( i960 (80960sx)) the synchronous microprocessor interface mode for the i960 (80960sx) is selected when mptype_im = 0 and mpmode_as = 1. interface timing for the synchronous mode write cycle is given in figure 16 and in table 55. interface timing for the read cycle is given in figure 17 and table 56 on page 67. figure 16. microprocessor interface mode 3?write cycle timings table 55. microprocessor interface mode 3?write cycle timing specifications symbol parameter min max unit tc pclk period 25 100 ns tcycle bus transfer cycle time 6 tc t141 cs_n asserted low to ta_n (ready) high delay ? 10 ns t142 cs_n asserted low setup to ts_n (ale) fall 10 ? ns t143 ds_n (as)/rw_n (w/r) asserted low setup to pclk rise 5 ? ns t144 ts_n (ale) high to fall setup 10 ? ns t145 address_n valid setup to ts_n (ale) fall 10 ? ns t146 address_n valid hold/data valid delay after ts_n (ale) fall 5 ? ns t147 ds_n (as) asserted low hold after pclk rise 0 ? ns t148 ts_n (ale) asserted low hold 5 ? tc t149 pclk rise to ta_n (ready) delay 2 10 ns t150 data_n valid hold after pclk rise 0 ? ns t151 cs_n asserted low hold after ts_n (ale) fall 6 ? tc t152 cs_n negated to ta_n (ready) 3-state delay ? 10 ns address_n (ad) cs_n ts_n (ale) ta_n (ready) t152 rw_n (w/r) high-z high-z t144 t145 t148 t149 valid pclk (clk2) tc data_n (ad) valid ds_n (as) t143 t146 t147 t149 t150 tcycle (input) inserted wait-states t151 t142 t141
agere systems inc. 67 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 11 microprocessor interface (continued) 11.3 microprocessor interface timing (continued) figure 17. microprocessor interface mode 3?read cycle timings table 56. microprocessor interface mode 3?read cycle timing specifications symbol parameter min max unit tcycle bus transfer cycle time 8 16* * the typical value for most register accesses is 8 tc. tc t153 pclk rise to data_n valid delay 2 16 ns t154 pclk rise to data_n 3-state delay 2 16 ns t155 rw_n (w/r) asserted low hold after pclk rise 0 ? ns t156 cs_n asserted low hold after ts_n (ale) fall 8 ? tc address_n (ad) cs_n ts_n (ale) ta_n (ready) t152 rw_n (w/r) t141 high-z high-z t144 t145 t148 t149 valid pclk (clk2) data_n (ad) ds_n (as) t142 t143 t146 t147 t149 high-z high-z valid t154 t155 (output) inserted wait-states t156 t153 tc tcycle
68 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 11 microprocessor interface (continued) 11.3 microprocessor interface timing (continued) 11.3.4 mode 4 (80c196, 8xc251) the asynchronous microprocessor interface mode for the 80c196 and 8xc251 is selected when mptype_im = 0 and mpmode_as = 0. interface timing for the asynchronous mode write cycle is given in figure 18 and in table 57. interface timing for the read cycle is given in figure 19 and table 58 on page 69. all microprocessor sig- nals to the device should be stable for at least the time of one cycle of pclk (tc) plus additional setup time to be safely detected by the device. in the case that the 80c196 is being used, one programmed wait state may be needed to ensure that the falling edge of ta_n (ready) gets captured early enough by the microprocessor. figure 18. microprocessor interface mode 4?write cycle timings table 57. microprocessor interface mode 4?write cycle timing specifications symbol parameter min max unit tc pclk period 10 100 ns t161 cs_n asserted low setup to ts_n (ale) fall 10 ? ns t162 cs_n asserted low to ta_n (ready) high delay ? 10 ns t163 ts_n (ale) high to fall setup 10 ? ns t164 address_n valid setup to ts_n (ale) fall 10 ? ns t165 address_n valid hold after ts_n (ale) fall 10 ? ns t166 ts_n (ale) fall setup to ds_n (wr) asserted low 0 ? ns t167 ds_n (wr) asserted low to ta_n (ready) asserted low delay 0 10 ns t168 ta_n (ready) asserted low to negated delay 6 8 tc t169 ds_n (wr) /rw_n (rd) negated hold tc + 5 ? ns t170 ds_n (wr) asserted low hold* * the rising edge of ds_n (wr) is expected to come after the rising edge of ta_n (ready). 7?tc t171 data_n valid setup to ds_n (wr) negated 10 ? ns t172 data_n valid hold after ds_n (wr) negated 5 ? ns t173 cs_n asserted low hold after ds_n (wr) negated 0 ? ns t174 cs_n negated to ta_n (ready) 3-state delay ? 10 ns cs_n ts_n (ale) ta_n (ready) data_n t174 ds_n (wr) t162 high-z high-z t161 t166 t168 t170 t167 valid address_n t164 valid t172 t171 t163 (input) t173 t169 t165
agere systems inc. 69 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 11 microprocessor interface (continued) 11.3 microprocessor interface timing (continued) figure 19. microprocessor interface mode 4?read cycle timings table 58. microprocessor interface mode 4?read cycle timing specifications 11.4 use of a synchronous microprocessor with the tfec0410g in asynchronous mode the use of a synchronous microprocessor (such as the m860/m8260) to communicate with a tfec0410g config- ured for asynchronous mode (mpmode = 2) requires one additional consideration. there is a difference between the operation of a synchronous processor (e.g., m860/m8260) and the asynchronous processors (e.g., 68360). in a synchronous processor, the data is latched on the same edge that detects the assertion of ta_n. in an asynchro- nous processor, the ta_n (dsack) signal is detected, and the data is latched one clock period later. in both cases, the tfec0410g meets the timing required by these two different microprocessors. however, a syn- chronous processor operating with the tfec0410g configured in asynchronous mode will have problems consis- tently latching the correct data. it will depend on the relationship between the two clocks. as is shown in figure 15 on page 65, the data is presented on the bus after ta_n is asserted. if the microprocessor has a rising edge within this window, it will capture incorrect data. to operate the tfec0410g in asynchronous mode with a synchronous processor, add a delay on the ta_n signal from the tfec0410g; otherwise, consider using synchronous mode. symbol parameter min max unit t175 ts_n (ale) fall setup to rw_n (rd) asserted low 0 ? ns t176 rw_n (rd) asserted low hold* * the rising edge of rw_n (rd) is expected to come after the rising edge of ta_n (ready). ? the typical value for most register accesses is 7 tc?10 tc. 9?ns t177 rw_n (rd) asserted low to data valid delay 7 24 ? tc t178 rw_n (rd) negated to data 3-state delay 0 16 ns t179 rw_n (rd) asserted low to ta_n (ready) asserted low delay 0 10 ns t180 ta_n (ready) asserted low to negated delay 8 25 tc cs_n ts_n (ale) ta_n (ready) data_n t174 rw_n (rd) t162 high-z high-z t161 t175 t180 t176 t179 valid address_n t164 valid t178 t177 t163 (input) t173 t169 t165 high-z high-z
70 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 12 outline diagram 12.1 792-pin pbgam1th 40.00 0.20 40.00 a1 ball t d h al f k b p m l j ah r c e y n u an g ad v am aj ag ae ac aa w ap ak af ab ar a a1 ball corner 0.20 corner 38.70 19 30 26 28 24 32 22 20 18 4 6 8 10 12 14 16 2 34 5 23 25 7 31 29 15 21 3 27 11 17 9 13 1 35 33 au at av aw 36 38 37 39 1.00 35.35 max + 0.70 ? 0.05 a1 ball pad indicator available marking area 17.72 8 x 4.33 4 x 45 35.35 max 38.70 + 0.70 ? 0.05 country of origin indicator chamfer 1.17 0.05 seating plane solder ball 0.61 0.06 0.20 2.28 0.21 0.50 0.10 30 typ 0.50 r, 3 places 1.00 1.00
agere systems inc. 71 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 13 list of acronyms a adm add/drop multiplexer ais alarm indication signal ais-l line alarm indication signal api application program interface apll analog phase locked loop ar alarm register au administrative unit (sdh naming for frames) b b1, b2, b3 error count bits bar base address register bch bose-chaudhuri-hocquenguem (weak fec cyclic code) bdi backward defect indication bdi-o backward defect indication overhead bdi-p backward defect indication payload bei backward error indication ber bit error rate bi backward indication bim byte interleaved multiplexer bip bit interleaved parity bip-8 bit interleaved parity level 8 bist built-in self-test bit binary digit bli backward line indication blsr bidirectional line switch ring bits/s bits per second bs boundary scan c c2 expected payload label bit cbr constant bit rate cdr clock data recovery cm common mode or configuration management or connection monitoring cmep connection monitoring end point cmf common-mode failure cml current-mode logic cmoh connection monitoring overhead cmr common mode rejection cms current-mode switching cmv common-mode voltage cntd continuous n-times detect cor clear on read corba common object request broker architecture cow clear on write cpt cell pointer table cpu central processing unit crc cyclic redundancy check or cyclic redundancy code cv coding violation cv-l line coding violation cv-p path coding violation cv-s section coding violation d dcc data communications channel dll delay-locked loop dpll dedicated phase-locked loop dram dynamic random access memory dsp digital signal processor dw digital wrapper dwac digital wrapper access channel dwdm dense wavelength division multiplexing dwsfec digital wrapper enhanced forward error correction e efec enhanced forward error correction es errored second or elastic store esd electrostatic discharge esf extended superframe esi end system identifier evt egress vc table extest external test exti expected trace identifier f fae field application engineer fas frame alignment signal fcbga flip-chip ball-grid array fcs frame check sequence fdi forward defect indication fdi-o forward defect indication overhead fdi-p forward defect indication payload fe framing (bit) error febe far-end block error fec forward error correction fifo first in, first out fm frequency modulation fpga field programmable gate array fs fixed stuff fsi fec status indicator fsm finite state machine ftfl fault type and fault location
72 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 13 list of acronyms (continued) g gbe gigabit ethernet gnd ground gpi general purpose input gpio general purpose input/output gpo general purpose output grst global reset gsr global set/reset h h1, h2 sonet signal payload pointer bits hdlc high-level data link control hec header error correction or header error control hsi high-speed interface hw hardware i i/o input/output iadi intra-domain interface iae incoming alignment error idi initial domain identifier irdi inter-domain interface irq interrupt request isr interrupt status register itu international telecommunications union j j1 trace byte jedec joint electronic devices engineering council jc stuff control byte jtag joint test access group k k1, k2 aps bits of sonet signal l ladi intradomain interface lan local area network lapi low-level application programming interface lb loopback lck locked led light emitting diode loc loss of clock lof loss of frame lofa loss of frame alignment loh line overhead lol loss of lock lom loss of multiframe alignment lop loss of pointer los loss of signal lotc loss of transmit clock lrdi interdomain interface lsb least significant bit/byte lsn least significant nibble lte line terminating equipment lv low voltage lvds low-voltage differential signal m mfas multiframe alignment signal mpi microprocessor interface mpif master processor interface ms multiplex section msb most significant bit/byte msi multiplex structure identifier msn most significant nibble mutex mutual exclusion mux multiplex or multiplexor n njo negative justification offset (negative justification byte) nrz nonreturn to zero nsa non-service affecting n-time detect a received value remains the same for n consecutive frames.
agere systems inc. 73 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 13 list of acronyms (continued) o oa&m operations administration and maintenance och optical channel (single) oci open connection indication oduk optical channel data unit oh overhead ohp overhead processor ohpi overhead processor insertion ohpm overhead processor monitoring omsn optical multiplex section overhead oms optical multiplexing section omu optical multiplexing unit onni optical transport network node interface ooa out of alignment oof out of frame oom out of multiframe alignment oos optical transport module overhead signal opu optical channel payload unit osc optical supervisory channel osi open system interconnect oth optical transport hierarchy otm optical transport module otm-0 optical transport module of order 0 otn optical transport network ots optical transmission section otsn optical transmission section overhead otuk optical channel transport unit p pa persistency alarm pbga plastic ball grid array pbgam plastic ball grid array multilayer pclk microprocessor clock pd phase detector pdi payload defect indication phy physical layer pjo positive justification offset byte pll phase-locked loop pm performance monitoring pmclk performance monitoring clock pmoh path monitoring overhead pn pseudo-random noise sequence or pseudo-random number (i.e., pn29) pnz positive/negative/zero poac path overhead access channel poh path overhead pos packet-over-sonet/sdh p-p peak to peak pp pointer processor ppll programmable phase-locked loop pram pointer random access memory prbs pseudo-random bit sequence psi payload structure identifier q qos quality of service r r/w read/write rai remote alarm indication rdi remote defect indicator rdi-l line remote defect indication rei remote error indication rei-l line remote error indication res reserved rn random number ro read only rs reed solomon (strong fec) rw read/write rx receive rz return to zero
74 agere systems inc. hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 13 list of acronyms (continued) s sa service affecting sclk system clock sd signal degrade sdh synchronous digital hierarchy sef severely errored frame serdes serializer/deserializer sf signal fail sfi serdes framer interface sfi-4 serdes framer interface level 4 sm section monitoring snmp simple network management protocol snr signal-to-noise ratio soh section overhead sonet synchronous optical network sonfec sonet forward error correction spa selected packet available spe sonet payload envelope spif slave processor interface stat status indication ste section terminating equipment swi software interrupt t ta transfer acknowledge t a ambient temperature tbd to be determined tc temperature coefficient or time constant or tandem connection t c case temperature tck test clock tcm tandem connection monitoring tcmoh tandem connection monitoring overhead tdi test data in tdm time division multiplexer tdmx transpose demultiplexer tdo test data out tea transfer error acknowledge tfec transmission forward error correcting tim trace identifier mismatch t j junction temperature tms test mode select toac transport overhead access channel toh transport overhead t prop propagation time trstn test reset (active low) ts time slot or tributary slot tsi time-slot interchange tsm tributary slot multiplexing tti trail trace identifier tx transmit u uneq unequipped uni user-network interface upsr unidirectional path switch ring utopia universal test and operations physical interface for atm v vbr variable bit rate vc virtual channel vci virtual connection indicator vco voltage-controlled oscillator vp virtual path vpi virtual path indicator vt virtual tributary vtg virtual tributary group w w1c write one clear wdm wavelength division multiplexing wrr weighted round robin x xpif external processor interface z z0 section overhead bit
agere systems inc. 75 hardware design guide july 2002 with strong/weak fec and digital wrapper tfec0410g 2.5/10 gbits/s optical networking interface 14 ordering information device code package temperature comcode (ordering number) TFEC0410G-3PBGA2 792-pin pbgam1th ?40 c to 85 c 700012029
copyright ? 2002 agere systems inc. all rights reserved july 2002 ds02 - 22 9 s o n t agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. agere, agere systems, and the agere logo are trademarks of agere systems inc. for additional information, contact your agere systems account manager or the following: internet: http://www.agere.com e-mail: docmaster@agere.com n. america: agere systems inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: agere systems hong kong ltd., suites 3201 & 3210-12, 32/f, tower 2, the gateway, harbour city, kowloon tel. (852) 3129-2000 , fax (852) 3129-2020 china: (86) 21-5047-1212 (shanghai), (86) 755-25881122 (shenzhen) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 6778-8833 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 7000 624624 , fax (44) 1344 488 045 eia is a registered trademark of the electronic industries association. ieee is a registered trademark of the institute of electrical and electronics engineers, inc. intel and i960 are registered trademarks of intel corporation. motorola is a registered trademark of motorola, inc.

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